Programmer’s Model

SMBCRx example configurations

Table 3-10 shows some example register configurations for the SMBCRx registers.

Table 3-10 SMBCRx example configurations

3.2.8Bank status registers SMBSR0-7

The eight SMBSRx registers show the status of each memory bank.

Programmer’s Model

Table 3-10 on page 3-16 shows the bit assignment of a SMBSRx register.

Writing a 1 to this bit clears the write protect error status flag.

Writing a 0 to this bit has no effect.

3.2.9SSMC status register, SSMCSR

The SSMCR register shows the current status of the external wait during an externally waited transfer. Table 3-12 shows the bit assignment of the SSMCR register.

Table 3-12 SSMCSR register bits

After an externally waited transfer that was terminated early, this bit value can be used to detect when SMWAIT is deasserted. At all other times this bit reads zero.

Programmer’s Model

3.2.10SSMC control register, SSMCCR

The SSMCCR register is used to control the SSMC. Settings in this register affect all banks. Table 3-12 on page 3-17 shows the bit assignment of the SSMCCR register.

3.2.11Peripheral identification registers, SSMCPeriphID0-3

The SSMCPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The read-only registers provide the following options of the peripheral:

PartNumber[11:0]

This is used to identify the peripheral. The product code 0x031 is used for the PrimeCell SSMC.

DesignerID[19:12] This is the identification of the designer. ARM Limited is 0x41 (ASCII A).

Revision[23:20]

This is the revision number of the peripheral. The revision number starts from 0 and is revision dependent.

Configuration[31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 3-1 on page 3-19 shows the bit assignment for the SSMCPeriphID0-3 registers.

Programmer’s Model

Figure 3-1 Peripheral identification register bit assignment

The four, 8-bit peripheral identification registers are described in the following sections:

•SSMCPeriphID0 register

•SSMCPeriphID1 register on page 3-20

•SSMCPeriphID2 register on page 3-20

•SSMCPeriphID3 register on page 3-20.

SSMCPeriphID0 register

The SSMCPeriphID0 register is hard-coded and the fields within the registers determine the reset value. Table 3-14 shows the bit assignment of the SSMCPeriphID0 register.