Добавил:

Andrey Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

Предмет:

Электротехника

Файл:

ARM PrimeCell synchronous static memory controller technical reference manual.pdf

Источник:

https://manualmachine.com

Скачиваний:

Добавлен:

23.08.2013

Размер:

1.4 Mб

Скачать

☆

<<< < Предыдущая 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 2829 / 3729 30 31 32 33 34 35 36 37 > Следующая >>>

Programmer’s Model

3.2PrimeCell SSMC registers

The PrimeCell SSMC control and status registers are shown in Table 3-1.

Note

SSMC RegBase is the base address of the SSMC bank registers.

Table 3-1 PrimeCell SSMC register summary

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

SSMC RegBase	Read/write	4	0xF	SMBIDCYR0	Idle cycle control register for memory
+ 0x00					bank 0. See Table 3-2 on page 3-9.

SSMC RegBase	Read/write	5	0x1F	SMBWSTRDR0	Read wait state control register for
+ 0x04					memory bank 0. See Table 3-3 on
					page 3-10.

SSMC RegBase	Read/write	5	0x1F	SMBWSTRR0	Write wait state control register for
+ 0x08					memory bank 0. See Table 3-4 on
					page 3-10.

SSMC RegBase	Read/write	4	0x1	SMBWSTOENR0	Output enable assertion delay control
+ 0x0C					register for memory bank 0. See
					Table 3-5 on page 3-11.

SSMC RegBase	Read/write	4	0x0	SMBWSTWENR0	Write enable assertion delay control
+ 0x10					register for memory bank 0. See
					Table 3-6 on page 3-11.

SSMC RegBase	Read/write	21	0x303020	SMBCR0	Control register for memory bank 0. See
+ 0x14					Table 3-9 on page 3-13.

SSMC RegBase	Read/write	1	0x0	SMBSR0	Status register for memory bank 0. See
+ 0x18					Table 3-11 on page 3-17.

SSMC RegBase	Read/write	5	0x1F	SMBWSTBRDR0	Burst read wait state control register for
+ 0x1C					memory bank 0. See Table 3-7 on
					page 3-12.

SSMC RegBase	Read/write	4	0x1F	SMBIDCYR1	Idle cycle control register for memory
+ 0x20					bank 1. See Table 3-2 on page 3-9.

ARM DDI 0236A

3-3

Programmer’s Model

Table 3-1 PrimeCell SSMC register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

SSMC RegBase	Read/write	5	0x1F	SMBWSTRDR1	Wait state 1 control register for memory
+ 0x24					bank 1. See Table 3-3 on page 3-10.

SSMC RegBase	Read/write	5	0x1F	SMBWSTWRR1	Wait state 2 control register for memory
+ 0x28					bank 1. See Table 3-4 on page 3-10.

SSMC RegBase	Read/write	4	0x0	SMBWSTOENR1	Output enable assertion delay control
+ 0x2C					register for memory bank 1. See
					Table 3-5 on page 3-11.

SSMC RegBase	Read/write	4	0x0	SMBWSTWENR1	Write enable assertion delay control
+ 0x30					register for memory bank 1. See
					Table 3-6 on page 3-11.

SSMC RegBase	Read/write	21	0x30300	SMBCR1	Control register for memory bank 1. See
+ 0x34					Table 3-9 on page 3-13.

SSMC RegBase	Read/write	1	0x0	SMBSR1	Status register for memory bank 1. See
+ 0x38					Table 3-11 on page 3-17.

SSMC RegBase	Read/write	5	0x1F	SMBWSTBRDR1	Burst read wait state control register for
+ 0x3C					memory bank 1. See Table 3-7 on
					page 3-12.

SSMC RegBase	Read/write	4	0xF	SMBIDCYR2	Idle cycle control register for memory
+ 0x40					bank 2. See Table 3-2 on page 3-9.

SSMC RegBase	Read/write	5	0x1F	SMBWSTRDR2	Read wait state control register for
+ 0x44					memory bank 2. See Table 3-3 on
					page 3-10.

SSMC RegBase	Read/write	5	0x1F	SMBWSTWRR2	Wait state control register for memory
+ 0x48					bank 2. See Table 3-4 on page 3-10.

SSMC RegBase	Read/write	4	0x0	SMBWSTOENR2	Output enable assertion delay control
+ 0x4C					register for memory bank 2. See
					Table 3-5 on page 3-11.

SSMC RegBase	Read/write	4	0x0	SMBWSTWENR2	Write enable assertion delay control
+ 0x50					register for memory bank 2. See
					Table 3-6 on page 3-11.

SSMC RegBase	Read/write	21	0x303010	SMBCR2	Control register for memory bank 2. See
+ 0x54					Table 3-9 on page 3-13.

3-4

ARM DDI 0236A

					Programmer’s Model
				Table 3-1 PrimeCell SSMC register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

SSMC RegBase	Read/write	1	0x0	SMBSR2	Status register for memory bank 2. See
+ 0x58					Table 3-11 on page 3-17.

SSMC RegBase	Read/write	5	0x1F	SMBWSTBRDR2	Burst read wait state control register for
+ 0x5C					memory bank 2. See Table 3-7 on
					page 3-12.

SSMC RegBase	Read/write	4	0xF	SMBIDCYR3	Idle cycle control register for memory
+ 0x60					bank 3. See Table 3-2 on page 3-9.

SSMC RegBase	Read/write	5	0x1F	SMBWSTRDR3	Read wait state control register for
+ 0x64					memory bank 3. See Table 3-3 on
					page 3-10.

SSMC RegBase	Read/write	5	0x1F	SMBWSTWRR3	Wait state control register for memory
+ 0x68					bank 3. See Table 3-4 on page 3-10.

SSMC RegBase	Read/write	4	0x0	SMBWSTOENR3	Output enable assertion delay control
+ 0x6C					register for memory bank 3. See
					Table 3-5 on page 3-11.

SSMC RegBase	Read/write	4	0x0	SMBWSTWENR3	Write enable assertion delay control
+ 0x70					register for memory bank 3. See
					Table 3-6 on page 3-11.

SSMC RegBase	Read/write	21	0x303000	SMBCR3	Control register for memory bank 3. See
+ 0x74					Table 3-9 on page 3-13.

SSMC RegBase	Read/write	1	0x0	SMBSR3	Status register for memory bank 3. See
+ 0x78					Table 3-11 on page 3-17.

SSMC RegBase	Read/write	5	0x1F	SMBWSBTRDR3	Burst read wait state control register for
+ 0x7C					memory bank 3. See Table 3-7 on
					page 3-12

SSMC RegBase	Read/write	4	0xF	SMBIDCYR4	Idle cycle control register for memory
+ 0x80					bank 4. See Table 3-2 on page 3-9.

SSMC RegBase	Read/write	5	0x1F	SMBWSTRDR4	Read wait state control register for
+ 0x84					memory bank 4. See Table 3-3 on
					page 3-10.

ARM DDI 0236A

3-5

Programmer’s Model

Table 3-1 PrimeCell SSMC register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

SSMC RegBase	Read/write	5	0x1F	SMBWSTWRR4	Write wait state control register for
+ 0x88					memory bank 4. See Table 3-4 on
					page 3-10.

SSMC RegBase	Read/write	4	0x0	SMBWSTOENR4	Output enable assertion delay control
+ 0x8C					register for memory bank 4. See
					Table 3-5 on page 3-11.

SSMC RegBase	Read/write	4	0x0	SMBWSTWENR4	Write enable assertion delay control
+ 0x90					register for memory bank 4. See
					Table 3-6 on page 3-11.

SSMC RegBase	Read/write	21	0x303020	SMBCR4	Control register for memory bank 4. See
+ 0x94					Table 3-9 on page 3-13.

SSMC RegBase	Read/write	1	0x0	SMBSR4	Status register for memory bank 4. See
+ 0x98					Table 3-11 on page 3-17.

SSMC RegBase	Read/write	5	0x1F	SMBWSTBRDR4	Read wait state control register for
+ 0x9C					memory bank 4. See Table 3-7 on
					page 3-12.

SSMC RegBase	Read/write	4	0xF	SMBIDCYR5	Idle cycle control register for memory
+ 0xA0					bank 5. See Table 3-2 on page 3-9.

SSMC RegBase	Read/write	5	0x1F	SMBWSTRDR5	Wait state control register for memory
+ 0xA4					bank 5. See Table 3-3 on page 3-10.

SSMC RegBase	Read/write	5	0x1F	SMBWSTWRR5	Write wait state control register for
+ 0xA8					memory bank 5. See Table 3-4 on
					page 3-10.

SSMC RegBase	Read/write	4	0x0	SMBWSTOENR5	Output enable assertion delay control
+ 0xAC					register for memory bank 5. See
					Table 3-5 on page 3-11.

SSMC RegBase	Read/write	4	0x0	SMBWSTWENR5	Write enable assertion delay control
+ 0xB0					register for memory bank 5. See
					Table 3-6 on page 3-11.

SSMC RegBase	Read/write	21	0x303020	SMBCR5	Control register for memory bank 5. See
+ 0xB4					Table 3-9 on page 3-13.

3-6

ARM DDI 0236A

					Programmer’s Model
				Table 3-1 PrimeCell SSMC register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

SSMC RegBase	Read/write	1	0x0	SMBSR5	Status register for memory bank 5. See
+ 0xB8					Table 3-11 on page 3-17.

SSMC RegBase	Read/write	5	0x1F	SMBWSTBRDR5	Read wait state control register for
+ 0xBC					memory bank 5. See Table 3-7 on
					page 3-12.

SSMC RegBase	Read/write	4	0xF	SMBIDCYR6	Idle cycle control register for memory
+ 0xC0					bank 6. See Table 3-2 on page 3-9.

SSMC RegBase	Read/write	5	0x1F	SMBWSTRDR6	Read wait state control register for
+ 0xC4					memory bank 6. See Table 3-3 on
					page 3-10.

SSMC RegBase	Read/write	5	0x1F	SMBWSTWRR6	Write wait state control register for
+ 0xC8					memory bank 6. See Table 3-4 on
					page 3-10.

SSMC RegBase	Read/write	4	0x0	SMBWSTOENR6	Output enable assertion delay control
+ 0xCC					register for memory bank 6. See
					Table 3-5 on page 3-11.

SSMC RegBase	Read/write	4	0x0	SMBWSTWENR6	Write enable assertion delay control
+ 0xD0					register for memory bank 6. See
					Table 3-6 on page 3-11.

SSMC RegBase	Read/write	21	0x303010	SMBCR6	Control register for memory bank 6. See
+ 0xD4					Table 3-9 on page 3-13.

SSMC RegBase	Read/write	1	0x0	SMBSR6	Status register for memory bank 6. See
+ 0xD8					Table 3-11 on page 3-17.

SSMC RegBase	Read/write	5	0x1F	SMBWSTBRDR6	Burst read wait state control register for
+ 0xDC					memory bank 6. See Table 3-7 on
					page 3-12.

SSMC RegBase	Read/write	4	0xF	SMBIDCYR7	Idle cycle control register for memory
+ 0xE0					bank 7. See Table 3-2 on page 3-9.

SSMC RegBase	Read/write	5	0x1F	SMBWSTRDR7	Read wait state control register for
+ 0xE4					memory bank 7. See Table 3-3 on
					page 3-10.

ARM DDI 0236A

3-7

Programmer’s Model

Table 3-1 PrimeCell SSMC register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

SSMC RegBase	Read/write	5	0x1F	SMBWSTWRR7	Write wait state control register for
+ 0xE8					memory bank 7. See Table 3-4 on
					page 3-10.

SSMC RegBase	Read/write	4	0x0	SMBWSTOENR7	Output enable assertion delay control
+ 0xEC					register for memory bank 7. See
					Table 3-5 on page 3-11.

SSMC RegBase	Read/write	4	0x0	SMBWSTWENR7	Write enable assertion delay control
+ 0xF0					register for memory bank 7. See
					Table 3-6 on page 3-11.

SSMC RegBase	Read/write	21	0x303000	SMBCR7	Control register for memory bank 7. See
+ 0xF4					Table 3-9 on page 3-13.

SSMC RegBase	Read/write	1	0x0	SMBSR7	Status register for memory bank 7. See
+ 0xF8					Table 3-11 on page 3-17.

SSMC RegBase	Read/write	5	0x1F	SMBWSTBRDR7	Burst read wait state control register for
+ 0xFC					memory bank 6. See Table 3-7 on
					page 3-12.

SSMC RegBase	Reserved	-	Undefined	Reserved	Reserved.
+ 0x100-0x1FC

SSMC RegBase	Read-only	1	0x0	SSMCSR	External wait status register for all
+ 0x200					memory banks. See Table 3-12 on
					page 3-17.

SSMC RegBase	Read/write	3	0x1	SSMCCR	SSMC control register. Controls all
+ 0x204					banks. See Table 3-13 on page 3-18.

SSMC RegBase	Read/write	1	0x0	SSMCITCR	SSMC test control register. See
+ 0x208					Table 4-1 on page 4-3.

SSMC RegBase	Read/write	7	System	SSMCITIP	SSMC test input register. See Table 4-2
+ 0x20C			dependent		on page 4-3.

SSMC RegBase	Read/write	2	System	SSMCITOP	SSMC test output register. See Table 4-3
+ 0x210			dependent		on page 4-4.

SSMC RegBase	Reserved	-	Undefined	Reserved	Reserved.
+ 0x214-0xFDC

3-8

ARM DDI 0236A

					Programmer’s Model
				Table 3-1 PrimeCell SSMC register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

SSMC RegBase	Read-only	8	0x93	SSMCPeriphID0	Peripheral ID register bits
+ 0xFE0					[7:0]. See Table 3-14 on page 3-19.

SSMC RegBase	Read-only	8	0x10	SSMCPeriphID1	Peripheral ID register bits [15:8]. See
+ 0xFE4					Table 3-15 on page 3-20.

SSMC RegBase	Read-only	8	0x04	SSMCPeriphID2	Peripheral ID register bits [23:16]. See
+ 0xFE8					Table 3-16 on page 3-20.

SSMC RegBase	Read-only	8	0x00	SSMCPeriphID3	Peripheral ID register bits [31:24]. See
+ 0xFEC					Table 3-17 on page 3-20.

SSMC RegBase	Read-only	8	0x0D	SSMCPCellID0	PrimeCell ID register bits
+ 0xFF0					[7:0]. See Table 3-18 on page 3-21.

SSMC RegBase	Read-only	8	0xF0	SSMCPCellID1	PrimeCell ID register bits [15:8]. See
+ 0xFF4					Table 3-19 on page 3-22.

SSMC RegBase	Read-only	8	0x05	SSMCPCellID2	PrimeCell ID register bits [23:16]. See
+ 0xFF8					Table 3-20 on page 3-22.

SSMC RegBase	Read-only	8	0xB1	SSMCPCellID3	PrimeCell ID register bits [31:24]. See
+ 0xFFC					Table 3-21 on page 3-22.

3.2.1Bank idle cycle control registers SMBIDCYR0-7

The eight SMBIDCYRx registers are the PrimeCell SSMC bank idle cycle control registers, that must be programmed for the configuration of the PrimeCell SSMC memory banks 0 to 7. Each register is identical in structure. Table 3-2 shows the bit assignment of an SMBIDCYRx register.

			Table 3-2 SMBIDCYRx register bits

Bits	Name	Type	Description

31:4	Reserved	-	Reserved, do not modify, read as zero, write as zero.

3:0	IDCY	Read/write	Idle or turnaround cycles. Defaults to 1111 at reset.
			This field controls the number of bus turnaround cycles added between read and write
			accesses to prevent bus contention on the external memory data bus.
			Turnaround time = IDCY x tHCLKa

ARM DDI 0236A

3-9

Programmer’s Model

a.tHCLK = period of SMMEMCLK.

3.2.2Bank read wait state control registers SMBWSTRDR0-7

The eight SMBWSTRDRx registers are the PrimeCell SSMC bank read wait state control registers, that must be programmed for the configuration of the PrimeCell SSMC memory banks 0 to 7. Each register is identical in structure. Table 3-3 shows the bit assignment of an SMBWSTRDRx register.

			Table 3-3 SMBWSTRDRx register bits

Bits	Name	Type	Description

31:5	Reserved	-	Reserved, do not modify, read as zero, write as zero.

4:0	WSTRD	Read/write	Read wait state. Defaults to 11111 at reset.
			For SRAM and ROM, the WSTRD field controls the number of wait states for read
			accesses, and the external wait assertion timing for reads.

For burst ROM, the WSTRD field controls the number of wait states for the first read access only.

Wait state time = WSTRD x tHCLKa

a.tHCLK = period of SMMEMCLK.

3.2.3Bank write wait state control registers SMBWSTWRR0-7

The eight SMBWSTWRRx registers are the PrimeCell SSMC bank write wait state control registers, that must be programmed for the configuration of the PrimeCell SSMC memory banks 0 to 7. Each register is identical in structure. Table 3-4 shows the bit assignment of an SMBWSTWRRx register.

			Table 3-4 SMBWSTWRRx register bits

Bits	Name	Type	Description

31:5	Reserved	-	Reserved, do not modify, read as zero, write as zero.

4:0	WSTWR	Read/write	Write wait state. Defaults to 11111 at reset.
			For SRAM, the WSTWR field controls the number of wait states for write accesses,
			and the external wait assertion timing for writes.

Wait state time = WSTWR x tHCLKa

WSTWR does not apply to read-only devices such as ROM.

a. tHCLK = period of SMMEMCLK

3-10

ARM DDI 0236A

Programmer’s Model

3.2.4Bank output enable assertion delay control registers SMBWSTOENR0-7

The eight SMBWSTOENRx registers are the PrimeCell SSMC bank output enable assertion delay control registers, that must be programmed for the configuration of the PrimeCell SSMC memory banks 0 to 7. Each register is identical in structure. Table 3-5 shows the bit assignment of an SMBWSTOENRx register.

			Table 3-5 SMBWSTOENRx register bits

Bits	Name	Type	Description

31:4	Reserved	-	Reserved, do not modify, read as zero, write as zero.

3:0	WSTOEN	Read/write	Output enable assertion delay from chip select assertion. Defaults to 0001 at reset.

3.2.5Bank write enable assertion delay control registers SMBWSTWENR0-7

The eight SMBWSTWENRx registers are the PrimeCell SSMC bank write enable assertion delay control registers, that must be programmed for the configuration of the PrimeCell SSMC memory banks 0 to 7. Each register is identical in structure. Table 3-6 shows the bit assignment of an SMBWSTWENRx register.

			Table 3-6 SMBWSTWENRx register bits

Bits	Name	Type	Description

31:4	Reserved	-	Reserved, do not modify, read as zero, write as zero.

3:0	WSTWEN	Read/write	Write enable assertion delay from chip select assertion. Defaults to 0000 at reset.

ARM DDI 0236A

3-11

Programmer’s Model

3.2.6Bank burst read wait delay control registers SMBWSTBRDR0-7

The eight SMBWSTBRDRx registers are the PrimeCell SSMC bank burst read wait state control registers, that must be programmed for the configuration of the PrimeCell SSMC memory banks 0 to 7. Each register is identical in structure. Table 3-7 shows the bit assignment of an SMBWSTBRDRx register.

			Table 3-7 SMBWSTBRDRx register bits

Bits	Name	Type	Description

31:4	Reserved	-	Reserved, do not modify, read as zero, write as zero.

3:0	WSTBRD	Read/write	Burst read wait state. Defaults to 1111 at reset.
			For burst devices, the WSTBRD field controls the number of wait states for the
			burst read accesses after the first read.

Wait state time = WSTWBRD x tHCLKa

WSTWBRD does not apply to nonburst devices.

a.tHCLK = period of SMMEMCLK

3.2.7Bank control registers SMBCR0-7

The eight SMBCRx registers are the PrimeCell SSMC bank control registers, that must be programmed for the configuration of the PrimeCell SSMC memory banks 0 to 7. Each register is identical in structure. Table 3-8 shows the memory bank default external memory width at reset.

Table 3-8 PrimeCell SSMC reset default memory width

	PrimeCell	Default memory
	SSMC	Default memory
	SSMC	width
	memory bank	width
	memory bank

	Bank 0	32-bit

	Bank 1	8-bit

	Bank 2	16-bit

	Bank 3	8-bit

	Bank 4	32-bit

3-12

ARM DDI 0236A

Programmer’s Model

Table 3-8 PrimeCell SSMC reset default memory width

	PrimeCell	Default memory
	SSMC	Default memory
	SSMC	width
	memory bank	width
	memory bank

	Bank 5	32-bit

	Bank 6	16-bit

	Bank 7	8-bit, or SMMWCS7[1:0] at reset

Note

If the system boots from a Bank7 external ROM device, then the memory width for that bank must be configured using the external control pins SMMWCS7[1:0] to provide the correct default external memory width at reset.

Table 3-9 shows the bit assignment of an SMBCRx register.

					Table 3-9 SMBCRx register bits

Bits	Name	Type	Description

31:22	Reserved	-	Reserved, do not modify, read as zero, write as zero.

21	BIWriteEn	Read/write	Controls the behavior of the SMBAA signal during write operations:
			0	= SMBAA=1 at all times
			1	= signal active for synchronous read accesses (default).

20	AddrValidWriteEn	Read/write	Controls the behavior of the signal SMADDRVALID during write
			operations:
			0	= signal always HIGH
			1	= signal active for asynchronous and synchronous write accesses
			(default).

19:18	BurstLenWrite	Read/write	Burst transfer length, used to set the number of sequential transfers
			supported by the burst device for a write:
			00		= 4-transfer burst (default)
			01		= 8-transfer burst
			10		= reserved
			11		= continuous burst (synchronous only).

ARM DDI 0236A

3-13

Programmer’s Model

				Table 3-9 SMBCRx register bits (continued)

Bits	Name	Type	Description

17	SyncWriteDev	Read/write	Synchronous access capable device connected. Access the device using
			synchronous accesses for writes:
			0	= asynchronous device (default)
			1	= synchronous device.

16	BMWrite	Read/write	Burst mode write:
			0	= nonburst writes to memory devices (default at reset)
			1	= burst mode writes to memory devices.

15:14	Reserved	-	Reserved, do not modify, read as zero, write as zero.

13	BIReadEn	Read/write	Controls the behavior of the signal SMBAA and SMIND signals during
			read operations.
			0	= SMBAA=1 and SMIND=1 at all times
			1	= Signals active for synchronous read accesses (default).

12	AddrValidReadEn	Read/write	Controls the behavior of the signal SMADDRVALID during read
			operations:
			0	= signal always HIGH
			1 = signal active for asynchronous and synchronous read accesses (default).

11:10	BurstLenRead	Read/write	Burst transfer length, used to set the number of sequential transfers
			supported by the burst device for a read:
			00 = 4-transfer burst (default)
			01 = 8-transfer burst
			10 = reserved
			11 = continuous burst (synchronous only).

9	SyncReadDev	Read/write	Synchronous access capable device connected. Access the device using
			synchronous accesses for reads:
			0	= asynchronous device (default)
			1	= synchronous device.

8	BMRead	Read/write	Burst mode read and asynchronous page mode:
			0	= nonburst writes to memory devices (default at reset)
			1	= burst mode writes to memory devices.

7:6	Reserved	-	Reserved, do not modify, read as zero, write as zero.

3-14

ARM DDI 0236A

				Programmer’s Model
				Table 3-9 SMBCRx register bits (continued)

Bits	Name	Type	Description

5:4	MW	Read/write	Memory width. Defaults to different values at reset for each bank, see
			Table 3-8 on page 3-12.
			00 = 8-bit
			01 = 16-bit
			10 = 32-bit
			11 = reserved.

3	WP	Read/write	Write protect:
			0	= no write protection, for example, SRAM or write enabled Flash (default
			at reset)
			1	= device is write protected, for example, ROM, burst ROM, read only
			Flash, or SRAM.

2	WaitEn	Read/write	External memory controller wait signal enable
			0	= the PrimeCell SSMC is not controlled by the external wait signal
			(default at reset).
			1	= the PrimeCell SSMC looks for the external wait input signal, SMWAIT.

1	WaitPol	Read/write	Polarity of the external wait input for activation:
			0	= the SMWAIT signal is active LOW (default at reset)
			1	= the SMWAIT signal is active HIGH.

0	RBLE	Read/write	Read byte lane enable:
			0 = nSMBLS[3:0] all deasserted HIGH during system reads from external
			memory. This is for 8-bit devices where the byte lane enable is connected to
			the write enable pin so must be deasserted during a read (default at reset).
			The nSMBLS signals are used as write enables in this configuration.
			1	= nSMBLS[3:0] all asserted LOW during system reads from external
			memory. This is for 16 or 32-bit devices where the separate write enable
			signal is used and the byte lane selects must be held asserted during a read.
			The nSMWEN signal is used as the write enable in this configuration.

ARM DDI 0236A

3-15

<<< < Предыдущая 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 2829 / 3729 30 31 32 33 34 35 36 37 > Следующая >>>

Соседние файлы в предмете Электротехника

#
23.08.2013576.81 Кб14ARM PrimeCell SDRAM controller technical reference manual.pdf
#
23.08.20131.11 Mб14ARM PrimeCell single master DMA controller technical reference manual.pdf
#
23.08.20131.21 Mб17ARM PrimeCell smart card interface technical reference manual.pdf
#
23.08.20131.18 Mб11ARM PrimeCell static memory controller technical reference manual.pdf
#
23.08.2013554.72 Кб22ARM PrimeCell synchronous serial port master and slave technical reference manual.pdf
#
23.08.20131.4 Mб19ARM PrimeCell synchronous static memory controller technical reference manual.pdf
#
23.08.2013581.82 Кб27ARM PrimeCell UART technical reference manual.pdf
#
23.08.2013406.5 Кб11ARM PrimeCell VC-SDRAM controller technical reference manual.pdf
#
23.08.2013777.71 Кб18ARM PrimeCell vectored interrupt controller technical reference manual.pdf
#
23.08.2013162.1 Кб12ARM vector floating point instruction set quick reference card.pdf
#
23.08.201316.95 Mб27Armstrong E.The J2EE 1.4 tutorial.2005.pdf