Functional Overview

2.2PrimeCell MMCI adapter

Figure 2-2 shows a simplified block diagram of the PrimeCell MMCI adapter.

MMCI adapter

Figure 2-2 PrimeCell MMCI Adapter

The PrimeCell MMCI adapter is a multimedia card bus master that provides an interface to the multimedia card stack. It consists of five subunits:

•Adapter register block on page 2-5

•Control unit on page 2-5

•Command path on page 2-6

•Data path on page 2-11

•Data FIFO on page 2-16.

Note

The adapter registers and FIFO use the APB bus clock domain. The control unit, command path, and data path use the PrimeCell MMCI adapter clock domain.

In Figure 2-2, the power connections are not shown for clarity.

Functional Overview

2.2.1Adapter register block

The adapter register block contains all system registers. This block also generates the signals that clear the static flags in the MMCIStatus register (see Table 3-15 on

page 3-13). The clear signals are generated when 1 is written into the corresponding bit location of the MMCIClear register (see Table 3-16 on page 3-14). The clear signal for flags generated in the MCLK domain is synchronized to that domain.

2.2.2Control unit

The control unit contains the power management functions and the card bus clock divider. Figure 2-3 shows a block diagram of the control unit.

There are three power phases:

•power-off

•power-up

•power-on.

The power management logic controls an external power supply unit, and disables the card bus output signals during the power-off or power-up phases. The power-up phase is a transition phase between the power-off and power-on phases, and allows an external power supply to reach the card bus operating voltage. A device driver is used to ensure that the PrimeCell MMCI remains in the power-up phase until the external power supply reaches the operating voltage.