Programmer’s Model

3.3Register descriptions

The following PrimeCell MMCI registers are described in this section:

•Power control register, MMCIPower on page 3-6

•Clock control register, MMCIClock on page 3-7

•Argument register, MMCIArgument on page 3-8

•Command register, MMCICommand on page 3-8

•Command response register, MMCIRespCommand on page 3-9

•Response registers, MMCIResponse0-3 on page 3-10

•Data timer register, MMCIDataTimer on page 3-10

•Data length register, MMCIDataLength on page 3-11

•Data control register, MMCIDataCtrl on page 3-11

•Data counter register, MMCIDataCnt on page 3-12

•Status register, MMCIStatus on page 3-13

•Clear register, MMCIClear on page 3-14

•Interrupt mask registers, MMCIMask0-1 on page 3-15

•FIFO counter register, MMCIFifoCnt on page 3-16

•Data FIFO register, MMCIFIFO on page 3-16

•Peripheral identification registers, MMCIPeriphID0-3 on page 3-17

•PrimeCell identification registers, MMCIPCellID0-3 on page 3-20.

Programmer’s Model

3.3.1Power control register, MMCIPower

The MMCIPower register controls an external power supply. You can switch the power on and off, and adjust the output voltage. Table 3-2 shows the bit assignment of the MMCIPower register.

When you switch the external power supply on, the software first enters the power-up phase, and waits until the supply output is stable before moving to the power-on phase. During the power-up phase, MMCIPWR is set HIGH. The card bus outlets are disabled during both phases.

You can set the supply output voltage using the voltage value on the MMCIVDD outputs. Because the operating voltage range can be any value between 2.0 and 3.6 volts, the encoding of the voltage bits in the power control register is application-specific.

Note

After a data write, data cannot be written to this register for three MCLK clock periods plus two PCLK clock periods.

Programmer’s Model

3.3.2Clock control register, MMCIClock

The MMCIClock register controls the MMCICLK output. Table 3-3 shows the bit assignment of the clock control register.

While the PrimeCell MMCI is in identification mode, the MMCICLK frequency must be less than 400 kHz. You can change the clock frequency to the maximum card bus frequency when relative card addresses are assigned to all cards.

Note

After a data write, data cannot be written to this register for three MCLK clock periods plus two PCLK clock periods.

Programmer’s Model

3.3.3Argument register, MMCIArgument

The MMCIArgument register contains a 32-bit command argument, which is sent to a card as part of a command message. Table 3-4 shows the bit assignment of the MMCIArgument register.

If a command contains an argument, it must be loaded into the argument register before writing a command to the command register.

3.3.4Command register, MMCICommand

The MMCICommand register contains the command index and command type bits:

•The command index is sent to a card as part of a command message

•The command type bits control the Command Path State Machine (CPSM). Writing 1 to the enable bit starts the command send operation, while clearing the bit disables the CPSM.

Table 3-5 shows the bit assignment of the MMCICommand register.