AMBA Test Methodology

6.6Example AMBA AHB test sequences

Example AHB test sequences are described under the following headings:

•Entering test mode

•Write test vectors on page 6-19

•Read transfers on page 6-20

•Control vector on page 6-21

•Burst vectors on page 6-22

•Read-to-write and write-to-read on page 6-23

•Exiting test mode on page 6-24.

6.6.1Entering test mode

In normal operating mode TREQA will be LOW, indicating that test access is not required and the test bus will be used as required for normal operation, which will usually be part of the external bus interface. Entering test mode allows test vectors to be applied externally that will cause transfers on the internal bus.

The following sequence, as illustrated in Figure 6-4, is required in order to enter test mode:

1.TREQA is asserted to request test bus access.

2.Test mode is entered when the TIC has been granted the internal bus and this is indicated by the assertion of the TACK signal.

3.At this point TCLK will become the source of the internal HCLK signal.

4.When test mode has been entered TREQB is asserted to initiate an address vector.

5.The TIC will not perform any internal transfers until a valid address vector has been applied.

AMBA Test Methodology

Figure 6-4 Test start sequence

A synchronous tester is not expected to poll TACK for the bus.

Normally the TREQA signal is asserted for a minimum number of cycles to guarantee access to the bus (completion of the longest wait-state peripheral access or the maximum number of cycles for all bus masters to have completed their current instruction).

AMBA Test Methodology

6.6.2Write test vectors

AMBA Test Methodology

6.6.3Read transfers

Figure 6-6 Read test vector

The following points apply when reading test vectors:

•The TREQA and TREQB signals are used in the same way as for a write transfer. Initially, TREQA/B are used to apply an address vector, in the following cycle they are used to indicate that a read transfer is required. For the first cycle of a read the TBUS must be tristate, which ensures that the external equipment driving TBUS has an entire cycle to tristate its buffers before the TIC will enable the on-chip buffers to drive out the read data.

•At the end of a burst of reads it is also necessary to allow time for bus turnaround. In this case the TIC must turn off the internal buffers and an entire cycle is allowed before the external test equipment starts to drive.

•The end of a burst of reads is indicated by both TREQA and TREQB being HIGH, as for an address vector. In fact they must indicate address vector for two cycles, which allows for both the turnaround cycle at the start of the burst and also the turnaround cycle at the end of the burst.