AMBA APB

5.8Interfacing rev D APB peripherals to rev 2.0 APB

When using a combination of peripherals, some designed to the revision 2.0 specification and others designed to previous revisions, it is recommended that a revision 2.0 bridge is used and the earlier version peripherals are converted for use with the new bridge.

This section shows how a single revision D peripheral may be converted to the latest version of the APB. If a number of peripherals are to be converted it is more efficient to perform the conversion in a single centralized block.

There are two fundamental differences between the rev D and rev 2.0 APB specifications:

•the timing of the strobe signal compared to the enable signal

•the point at which read data is sampled.

To quickly determine whether a peripheral is designed to the rev D or rev 2.0 specification, see if it has a PSTB input (in which case it is rev D) or a PENABLE input (in which case it is rev 2.0). Figure 5-17 shows the two stages that are required to interface an existing revision D peripheral.

Firstly, the PSEL signal may be used to generate a PSTB signal. A fed-back version of the PSTB signal can be used to ensure the signal is only asserted for a single clock cycle.

The second interface stage that may be required is a falling edge triggered register or transparent latch on the output data (read data) from the peripheral. This is only required if the peripheral changes the output data after the falling edge.