AMBA AHB
3.19 AHB bus master
An AHB bus master has the most complex bus interface in an AMBA system. Typically an AMBA system designer would use predesigned bus masters and therefore would not need to be concerned with the detail of the bus master interface.
3.19.1Interface diagram
The interface diagram of an AHB bus master shows the main signal groups.
HBUSREQx
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HLOCKx |
Arbiter |
Arbiter |
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HGRANTx |
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grant |
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HTRANS[1:0] |
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Transfer type |
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Transfer |
HREADY |
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HRESP[1:0] |
HADDR[31:0] |
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response |
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AHB |
HWRITE |
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Reset |
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master |
Address |
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HRESETn |
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and |
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HSIZE[2:0] |
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Clock |
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control |
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HCLK |
HBURST[2:0] |
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HPROT[3:0] |
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Data |
HRDATA[31:0] |
HWDATA[31:0] |
Data |
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Figure 3-27 AHB bus master interface diagram
3.19.2Bus master timing diagrams
The following diagrams show the timing parameters related to an AHB bus master operating in an AMBA system:
•Figure 3-28 shows the AHB master reset timing parameters
•Figure 3-29 shows the AHB master transfer timing parameters
•Figure 3-30 shows the AHB master arbitration timing parameters.
HCLK
HRESETn
Tisrst
Tihrst
Figure 3-28 AHB master reset timing parameters
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© Copyright ARM Limited 1999. All rights reserved. |
3-49 |
AMBA AHB
HCLK |
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HTRANS[1:0] |
NONSEQ |
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Tovtr |
Tohtr |
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HADDR[31:0] |
A |
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HWRITE Tova |
Toha |
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HSIZE[2:0] |
Control |
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HBURST[2:0] |
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HPROT[3:0]Tovctl |
Tohctl |
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HWDATA[31:0] |
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Data |
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(A) |
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Tovwd |
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Tohwd |
HREADY |
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Tihrdy |
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Tisrdy |
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HRESP[1:0] |
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OKAY |
OKAY |
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Tihrsp |
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Tisrsp |
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HRDATA[31:0] |
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Data |
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(A) |
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Tihrd |
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Tisrd |
Figure 3-29 AHB master transfer timing parameters |
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HCLK |
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HBUSREQx |
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Tovreq |
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Tohreq |
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HLOCKx |
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Tovlck |
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Tohlck |
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HGRANTx |
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Tihgnt |
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Tisgnt |
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Figure 3-30 AHB master arbitration timing parameters
3-50 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM IHI 0011A |
AMBA AHB
3.19.3Timing parameters
The timing parameters related to an AHB bus master operating in an AMBA system are also shown in textual form in the following two tables. Table 3-10 details the input signals. Table 3-11 details output signals.
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Table 3-10 Bus master input timing parameters |
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Parameter |
Description |
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Tclk |
HCLK minimum clock period time |
Tisrst |
Reset deasserted setup time before HCLK |
Tihrst |
Reset deasserted hold time after HCLK |
Tisgnt |
HGRANTx setup time before HCLK |
Tihgnt |
HGRANTx hold time after HCLK |
Tisrdy |
Ready setup time before HCLK |
Tihrdy |
Ready hold time after HCLK |
Tisrsp |
Response setup time before HCLK |
Tihrsp |
Response hold time after HCLK |
Tisrd |
Read data setup time before HCLK |
Tihrd |
Read data hold time after HCLK |
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Table 3-11 Bus master output timing parameters |
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Parameter |
Description |
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Tovtr |
Transfer type valid time after HCLK |
Tohtr |
Transfer type hold time after HCLK |
Tova |
Address valid time after HCLK |
Toha |
Address hold time after HCLK |
Tovctl |
Control signal valid time after HCLK |
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© Copyright ARM Limited 1999. All rights reserved. |
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AMBA AHB
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Table 3-11 Bus master output timing parameters (continued) |
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Parameter |
Description |
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Tohctl |
Control signal hold time after HCLK |
Tovwd |
Write data valid time after HCLK |
Tohwd |
Write data hold time after HCLK |
Tovreq |
Request valid time after HCLK |
Tohreq |
Request hold time after HCLK |
Tovlck |
Lock valid time after HCLK |
Tohlck |
Lock hold time after HCLK |
3-52 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM IHI 0011A |