eZ80® CPU User Manual

313

OTIM

Output to I/O and Increment

Operation

({UU, 00h,C}) ← (HL)

B← B–1

C← C+1 HL ← HL+1

Description

The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to the I/O address specified by the C register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements. The C and HL registers increment.

Condition Bits Affected

Attributes

eZ80® CPU User Manual

314

OTIMR

Output to I/O and Increment

Operation

repeat {

({UU, 00h, C}) ← (HL)

B← B–1

C← C+1 HL ← HL+1

}while B ≠ 0

Description

The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to the I/O address specified by the C register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements. The C and HL registers increment. The instruction repeats until the B register equals 0.

Condition Bits Affected

eZ80® CPU User Manual

315

Attributes

eZ80® CPU User Manual

316

OTIR

Output to I/O and Increment

Operation

repeat {

({UU, BC[15:0]}) ← (HL) B ← B–1

HL ← HL+1 } while B ≠ 0

Description

The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements and the HL register increments. The instruction repeats until the B register equals 0.

Condition Bits Affected

S Not affected.

Z Set if B–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is logical 1; reset otherwise.

C Not affected.

Attributes