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LDDR

Load and Decrement with Repeat

Operation

repeat {

(DE) ← (HL) BC ← BC–1 DE ← DE–1 HL ← HL–1 } while (BC ≠ 0)

Description

The CPU writes the contents of the memory location with address contained in the multibyte register HL to the memory location with address contained in the multibyte register DE. The BC, DE, and HL registers decrement. This operation is repeated until BC decrements to 0.

In Z80 mode, the BC register is 16 bits, which allows the LDDR instruction to repeat a maximum of 65536 (64K) times. In ADL mode, the BC register is 24 bits, which allows the LDDR instruction to repeat a maximum of 16,777,216 (16M) times.

Condition Bits Affected

S Not affected.

Z Not affected.

H Reset.

P/V Reset if BC−1=0; set otherwise.

N Reset.

C Not affected.

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Attributes

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LDI

Load and Increment

Operation

(DE) ← (HL) BC ← BC–1 DE ← DE+1 HL ← HL+1

Description

The CPU writes the contents of the memory location with address contained in the multibyte register HL to the memory location with address contained in the multibyte register DE. The BC register decrements. The DE and HL registers increment.

Condition Bits Affected

S Not affected.

Z Not affected.

H Reset.

P/V Reset if BC−1=0; set otherwise.

N Reset.

C Not affected.

Attributes

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LDIR

Load and Increment with Repeat

Operation

repeat {

(DE) ← (HL) BC ← BC–1 DE ← DE+1 HL ← HL+1 } while (BC ≠ 0)

Description

The CPU writes the contents of the memory location with the address contained in the multibyte register HL to the memory location with the address contained in the multibyte register DE. The BC register decrements, and the DE and HL registers increment. This operation is repeated until BC decrements to 0.

In Z80 mode, the BC register is 16 bits, which allows the CPDR instruction a maximum of 65536 (64K) times. In ADL mode, the BC register is 24 bits, which allows the CPDR instruction to repeat a maximum of 16,777,216 (16M) times.

Condition Bits Affected

S Not affected.

Z Not affected.

H Reset.

P/V Reset if BC−1=0; set otherwise.

N Reset.

C Not affected.

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Attributes

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LEA IX/Y, IX+d

Load Effective Address

Operation

IX/Y ← IX+d

Description

The CPU adds the contents of the IX register to the signed displacement d and writes the sum to the specified multibyte Index Register, IX or IY.

Condition Bits Affected

None.

Attributes

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LEA IX/Y, IY+d

Load Effective Address

Operation

IX/Y ← IY+d

Description

The CPU adds the contents of the IY register to the two’s-complement displacement d and writes the sum to the specified multibyte Index Register, IX or IY.

Condition Bits Affected

None.

Attributes

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LEA rr, IX+d

Load Effective Address

Operation

rr ← IX+d

Description

The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU adds the contents of the IX register to the signed displacement d and writes the sum to the multibyte rr register.

Condition Bits Affected

None.

Attributes

kk identifies either the BC, DE, or HL multibyte register and is assembled into one of the Op Codes indicated in Table 73.

Table 73. Register and kk Op Codes for LEA rr, IX+d Instruction (hex)

Register kk

BC 02

DE 12

HL 22

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LEA rr, IY+d

Load Effective Address

Operation

rr ← IY+d

Description

The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU adds the contents of the IY register to the signed displacement d and writes the sum to the multibyte rr register.

Condition Bits Affected

None.

Attributes

kk identifies either the BC, DE, or HL multibyte register and is assembled into one of the Op Codes indicated in Table 74.

Table 74. Register and kk Op Codes for LEA rr, IY+d Instruction (hex)

Register kk

BC 03

DE 13

HL 23

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MLT rr

Multiply Register

Operation

rr[15:0] ← rr[15:8] x rr[7:0]

Description

The rr operand is any of the multibyte CPU registers BC, DE, or HL. The MLT instruction performs an 8-bit by 8-bit multiply operation. The rr operand Low byte is multiplied by the rr operand High byte. The 16-bit product is written back into the 16-bit rr register pair. The MLT instruction performs an 8-bit by 8-bit multiply operation with a 16-bit result, regardless of the ADL mode.

Condition Bits Affected

None.

Attributes

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MLT SP

Multiply Stack Pointer

Operation

SP[15:0] ← SP[15:8] x SP[7:0]

Description

The MLT SP instruction performs an 8-bit by 8-bit multiply operation using the Stack Pointer (SP). The SP Low byte is multiplied by the SP High byte. The 16-bit product is written back into the SP register. This operation is an 8-bit by 8-bit operation with a 16-bit result, regardless of the ADL mode. In ADL mode, or if the .L suffix is employed, the 24-bit Stack Pointer Long (SPL) is used. In Z80 mode, or if the .S suffix is employed, the 16-bit Stack Pointer Short (SPS) is used.

Condition Bits Affected

None.

Attributes

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NEG

Negate Accumulator

Operation

A ← 0–A

Description

The contents of the accumulator, A, are negated (two’s-complemented) and are identical to a subtraction of the accumulator from 0.

Condition Bits Affected

Attributes

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NOP

No Operation

Operation

No operation.

Description

The CPU performs no operation during execution of this instruction.

Condition Bits Affected

None.

Attributes

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OR A, (HL)

Logical OR

Operation

A ←A OR (HL)

Description

The (HL) operand is the 8-bit value located at the memory location specified by the contents of the multibyte CPU register HL. This 8-bit value is logically ORed to the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

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OR A, ir

Logical OR

Operation

A ←A OR ir

Description

The rr operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The rr operand is logically ORed to the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

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OR A, (IX/Y+d)

Logical OR

Operation

A ←A OR (IX/Y+d)

Description

The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-com- plement displacement d. This 8-bit value is logically ORed to the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

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OR A, n

Logical OR

Operation

A ←A OR n

Description

The 8-bit immediate value n is logically ORed to the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

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OR A, r

Logical OR

Operation

A ←A OR r

Description

The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is logically ORed to the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 75.

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Table 75. Register and jj Op Codes for OR A, r Instruction (hex)

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OTD2R

Output to I/O and Decrement with Repeat

Operation

repeat {

({UU, DE[15:0]}) ← (HL) BC ← BC–1

DE ← DE–1

HL ← HL–1 } while BC ≠ 0

Description

The CPU loads the contents of the memory location specified by the multibyte HL register into CPU memory. This byte is output to I/O address {UU, DE[15:0]}. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The BC, DE, and HL registers are decremented. The instruction repeats until the BC register equals 0.

Condition Bits Affected

S Not affected.

Z Set if BC–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is logical 1; reset otherwise.

C Not affected.

Attributes

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Note

This instruction operates differently in the eZ80190 device. In the eZ80190, operation is:

repeat {

({UU, BC[15:0]}) ← (HL)

B← B–1

C← C–1 HL ← HL–1

}while B ≠ 0