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Файл:Eden20v115.pdf
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- •datasheet outline
- •basic features
- •processor versions
- •competitive comparisons
- •compatibility
- •introduction
- •component summary
- •general architecture & features
- •instruction fetch
- •instruction decode
- •branch prediction
- •integer unit
- •d-cache & datapath
- •l2 cache
- •fp unit
- •mmx unit
- •3dnow! unit
- •general
- •additional functions
- •general
- •standard cpuid instruction functions
- •extended cpuid instruction functions
- •processor identification
- •edx value after reset.
- •control register 4 (cr4)
- •Machine-Specific Registers
- •omitted functions
- •bus interface
- •differences
- •clarifications
- •omissions
- •ball description
- •power management
- •bist
- •jtag
- •debug port
- •ac timing tables
- •dc specifications
- •recommended operating conditions
- •maximum ratings
- •dc characteristics
- •power dissipation
- •ebga package
- •introduction
- •typical environments
- •measuring tC and tJ
- •measuring tJ
- •estimating tC
VIA Eden ESP Processor Datasheet |
Preliminary Information |
January 2002
4.4.2 JTAG
The VIA Eden ESP processor has a JTAG scan interface that is used for test functions and the proprietary Debug Port. However, the VIA Eden ESP does not provide a fully compatible IEEE 1149.1 JTAG function.
From a practical user viewpoint, JTAG does not exist and the associated balls (TCLK, and so forth) should not be used.
4.4.3 DEBUG PORT
Certain processors have a proprietary Debug Port which uses the JTAG scan mechanism to control internal debug features (“probe mode”). These interfaces are not documented and are available (if at all) only under a non-disclosure agreement.
The VIA Eden ESP processor does not have a debug interface.
4-8 |
Hardware Interface |
Section 4 |
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