Programmer’s Model
3.3Summary of PrimeCell SMDMAC registers
The PrimeCell SMDMAC registers are shown in Table 3-1.
Table 3-1 PrimeCell SMDMAC register summary
Address |
Type |
Width |
Reset |
Name |
Description |
|
value |
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SMDMAC base |
Read |
2 |
0x0 |
DMACIntStatus |
This register provides the |
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+ 0x000 |
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interrupt status of the PrimeCell |
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SMDMAC. A HIGH bit |
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indicates that a specific DMA |
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channel interrupt is active. |
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SMDMAC base |
Read |
2 |
0x0 |
DMACIntTCStatus |
This register is used to determine |
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+ 0x004 |
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whether an interrupt was |
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generated due to the transaction |
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completing (terminal count). A |
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HIGH bit indicates that the |
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transaction completed. |
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SMDMAC base |
Write |
2 |
- |
DMACIntTCClear |
When writing to this register, |
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+ 0x008 |
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each data bit that is HIGH causes |
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the corresponding bit in the |
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DMACIntTCStatus and |
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DMACRawIntTCStatus registers |
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to be cleared. Data bits that are |
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LOW have no effect on the |
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corresponding bit in the register. |
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SMDMAC base |
Read |
2 |
0x0 |
DMACIntErrorStatus |
This register is used to determine |
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+ 0x00C |
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whether an interrupt was |
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generated due to an error being |
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generated. |
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SMDMAC base |
Write |
2 |
- |
DMACIntErrClr |
When writing to this register, |
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+ 0x010 |
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each data bit that is HIGH causes |
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the corresponding bit in the |
DMACIntErrorStatus and DMACRawIntErrorStatus registers to be cleared. Data bits that are LOW have no effect on the corresponding bit in the register.
3-6 |
Copyright © 2001 ARM Limited. All rights reserved. |
ARM DDI 0218B |
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Programmer’s Model |
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Table 3-1 PrimeCell SMDMAC register summary (continued) |
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Address |
Type |
Width |
Reset |
Name |
Description |
|
value |
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SMDMAC base |
Read |
2 |
- |
DMACRawIntTCStatus |
This register provides the raw |
|
+ 0x014 |
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status of DMA terminal count |
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interrupts prior to masking. A |
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HIGH bit indicates that the |
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interrupt request is active prior to |
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masking. |
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SMDMAC base |
Read |
2 |
- |
DMACRawIntErrorStatus |
This register provides the raw |
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+ 0x018 |
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status of DMA error interrupts |
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prior to masking. A HIGH bit |
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indicates that the interrupt |
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request is active prior to |
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masking. |
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SMDMAC base |
Read |
2 |
0x0 |
DMACEnbldChns |
This register shows which DMA |
|
+ 0x01C |
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channels are enabled. A HIGH |
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bit indicates that a DMA channel |
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is enabled. |
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SMDMAC base |
Read/write |
16 |
0x0000 |
DMACSoftBReq |
This register allows DMA burst |
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+ 0x020 |
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requests to be generated by |
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software. |
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SMDMAC base |
Read/write |
16 |
0x0000 |
DMACSoftSReq |
This register allows DMA single |
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+ 0x024 |
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requests to be generated by |
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software. |
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SMDMAC base |
Read/write |
16 |
0x0000 |
DMACSoftLBReq |
This register allows DMA last |
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+ 0x028 |
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burst requests to be generated by |
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software. |
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SMDMAC base |
Read/write |
16 |
0x0000 |
DMACSoftLSReq |
This register enables SMDMAC |
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+ 0x02C |
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DMA last single requests to be |
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generated by software. |
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SMDMAC base |
Read/write |
2 |
0b000 |
DMACConfiguration |
This register is used to configure |
|
+0x030 |
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the PrimeCell SMDMAC. |
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SMDMAC base |
Read/write |
16 |
0x0000 |
DMACSync |
This register enables or disables |
|
+ 0x34 |
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synchronization logic for the |
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DMA request signals. |
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SMDMAC base |
Read/write |
32 |
0x00000000 |
DMACC0SrcAddr |
DMA channel 0 source address. |
|
+0x100 |
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ARM DDI 0218B |
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Copyright © 2001 ARM Limited. All rights reserved. |
3-7 |
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Programmer’s Model
Table 3-1 PrimeCell SMDMAC register summary (continued)
Address |
Type |
Width |
Reset |
Name |
Description |
|
value |
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SMDMAC base |
Read/write |
32 |
0x00000000 |
DMACC0DestAddr |
DMA channel 0 destination |
|
+ 0x104 |
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address. |
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SMDMAC base |
Read/write |
31 |
0x00000000 |
DMACC0LLI |
DMA channel 0 linked list |
|
+ 0x108 |
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address. |
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SMDMAC base |
Read/write |
30 |
0x00000000 |
DMACC0Control |
DMA channel 0 control. |
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+ 0x10C |
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SMDMAC base |
Read/write |
19 |
0x00000 |
DMACC0Configuration |
DMA channel 0 configuration |
|
+ 0x110 |
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register. |
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SMDMAC base |
Read/write |
32 |
0x00000000 |
DMACC1SrcAddr |
DMA channel 1 source address. |
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+ 0x120 |
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SMDMAC base |
Read/write |
32 |
0x00000000 |
DMACC1DestAddr |
DMA channel 1 destination |
|
+ 0x124 |
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address. |
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SMDMAC base |
Read/write |
31 |
0x00000000 |
DMACC1LLI |
DMA channel 1 linked list |
|
+ 0x128 |
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address. |
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SMDMAC base |
Read/write |
30 |
0x00000000 |
DMACC1Control |
DMA channel 1 control. |
|
+ 0x12C |
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SMDMAC base |
Read/write |
19 |
0x00000 |
DMACC1Configuration |
DMA channel 1 configuration |
|
+ 0x130 |
|
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register. |
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SMDMAC base |
Read |
8 |
0x81 |
DMACPeriphID0 |
Peripheral identification register |
|
+0xFE0 |
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bits [7:0]. |
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SMDMAC base |
Read |
8 |
0x10 |
DMACPeriphID1 |
Peripheral identification register |
|
+0xFE4 |
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bits [15:8]. |
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SMDMAC base |
Read |
8 |
0x04 |
DMACPeriphID2 |
Peripheral identification register |
|
+0xFE8 |
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bits [23:16]. |
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SMDMAC base |
Read |
8 |
0x00 |
DMACPeriphID3 |
Peripheral identification register |
|
+0xFEC |
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bits [31:24]. |
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SMDMAC base |
Read |
8 |
0x0D |
DMACPCellID0 |
PrimeCell identification register |
|
+0xFF0 |
|
|
|
|
bits [7:0]. |
3-8 |
Copyright © 2001 ARM Limited. All rights reserved. |
ARM DDI 0218B |
|
|
|
|
|
Programmer’s Model |
|
|
|
|
|
Table 3-1 PrimeCell SMDMAC register summary (continued) |
||
|
|
|
|
|
|
|
Address |
Type |
Width |
Reset |
Name |
Description |
|
value |
||||||
|
|
|
|
|
||
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|
|
|
SMDMAC base |
Read |
8 |
0xF0 |
DMACPCellID1 |
PrimeCell identification register |
|
+0xFF4 |
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bits [15:8]. |
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SMDMAC base |
Read |
8 |
0x05 |
DMACPCellID2 |
PrimeCell identification register |
|
+0xFF8 |
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bits [23:16]. |
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SMDMAC base |
Read |
8 |
0xB1 |
DMACPCellID3 |
PrimeCell identification register |
|
+ 0xFFC |
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bits [31:24]. |
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|
ARM DDI 0218B |
Copyright © 2001 ARM Limited. All rights reserved. |
3-9 |