DMA Interface

B.5 Signal timing

The timing behavior of the DMA signals is as follows:

DMA request signal DMAC{L}(B/S)REQx

Informs the PrimeCell SMDMAC that a peripheral is ready to proceed with a DMA transfer of the indicated size.

Active HIGH. Sampled by the PrimeCell SMDMAC on the positive edge of HCLK. The DMA request signals are used in conjunction with the DMACCLR signal to perform handshaking.

DMA Acknowledge or Clear DMACCLRx

Indicates to the slave that a DMA transfer has completed.

Active HIGH.

DMA Terminal Count DMACTCx

Indicates to the slave that the end of packet has been reached.

Active HIGH.

Note

If the DMA request source does not use the same clock as the PrimeCell SMDMAC, then the request must be synchronized by setting the relevant bit in the DMACSync register.

DMA Interface

B.6 Functional timing diagram

A peripheral asserts a DMA request and holds it active. The DMACCLR signal is asserted by the PrimeCell SMDMAC when the last data item has been transferred. When the peripheral sees that the DMACCLR signal has gone active it takes the DMA request signal inactive. The PrimeCell DMAC controller deasserts the DMACLR signal when the DMA request signal goes inactive.

HCLK/PCLK

DMACREQ

DMACCLR

Valid

DMACTC

Figure B-23 DMA interface timing

DMA Interface