- •Preface
- •About this document
- •Intended audience
- •Organization
- •Typographical conventions
- •Timing diagram conventions
- •Further reading
- •ARM publications
- •Feedback
- •Feedback on this document
- •Feedback on the ARM PrimeCell SDRAM Controller
- •Introduction
- •1.1 About the ARM PrimeCell SDRAM Controller (PL170)
- •1.1.1 General information
- •1.1.2 Features of the PrimeCell SDRAM Controller
- •Functional Overview
- •2.1 ARM PrimeCell SDRAM Controller (PL170) overview
- •2.1.1 PrimeCell SDRAM control engine
- •Arbitration
- •2.1.2 Main AHB interface
- •Control registers
- •2.1.3 Optional features
- •Merging write buffer
- •Read buffer
- •2.1.4 Additional AHB ports
- •2.1.5 Pad interface
- •2.2 Overview of a Primecell SDRAM, ASIC/ASSP, unified memory system
- •2.2.1 External bus
- •2.2.2 Internal bus
- •Multi-port access
- •Clock domains
- •Maintaining memory during low-power sleep modes
- •2.2.4 Example signal waveforms
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Summary of PrimeCell SDRAM Controller registers
- •3.3 Register descriptions
- •3.3.1 Configuration registers
- •Configuration register 0
- •Configuration register 1
- •3.3.2 Refresh timer register
- •3.4 System initialization
- •3.5 Address mapping
- •3.5.1 Remapping the AMBA address to the SDRAM address bus
- •A.1 On-chip signals
- •A.1.1 AMBA AHB signals
- •A.1.2 Miscellaneous
- •A.2 Off-chip signals
- •A.2.1 SDRAM memory interface signals
- •First group
- •Second group
- •Third group
- •B.1 Commands
ARM PrimeCell SDRAM Controller (PL170) Signal Descriptions
A.2 Off-chip signals
The off-chip signals are shown in Table A-3.
|
|
|
Table A-3 Off-chip signals |
|
|
|
|
|
|
Signal |
Type |
Source/ |
Function |
|
destination |
||||
|
|
|
||
|
|
|
|
|
CLKOut |
Output |
Pad |
SDRAM clock |
|
|
|
|
|
|
CLKIn |
Input |
Pad |
External SDRAM clock |
|
|
|
|
|
|
CKEOut[3:0] |
Output |
Pad |
SDRAM clock enables |
|
|
|
|
|
|
nCSOut[3:0] |
Output |
Pad |
SDRAM chip selects |
|
|
|
|
|
|
AddrOut[14:0] |
Output |
Pad/ |
Address output for SDRAMs |
|
|
|
multiplexor |
|
|
|
|
|
|
|
nRASOut |
Output |
Pad |
Row address strobe |
|
|
|
|
|
|
nCASOut |
Output |
Pad |
Column address strobe |
|
|
|
|
|
|
nWEOut |
Output |
Pad |
Write enable |
|
|
|
|
|
|
DataIn[31:0] |
Input |
Pad/ |
Read data from the SDRAMs |
|
|
|
multiplexor |
|
|
|
|
|
|
|
DataOut[31:0] |
Output |
Pad/ |
Data output to SDRAMs |
|
|
|
multiplexor |
|
|
|
|
|
|
|
DQMOut[3:0] |
Output |
Pad |
Data mask output to SDRAMs |
|
|
|
|
|
|
DataEn |
Output |
Pad/ |
Data enable for write transfers |
|
|
|
multiplexor |
|
|
|
|
|
|
|
ExtBusReq |
Output |
Pad arbiter |
External address/data bus request |
|
|
|
|
|
|
ExtBusGnt |
Input |
Pad arbiter |
External address/data bus grant |
|
|
|
|
|
|
ExtCtlReq |
Output |
Pad arbiter |
External control bus request |
|
|
|
|
|
|
ExtCtlGnt |
Input |
Pad arbiter |
External control bus grant |
|
|
|
|
|
ARM DDI 0159D |
Copyright © ARM Limited 1999-2001. All rights reserved. |
A-5 |