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ARM PrimeCell RTC technical reference manual.pdf
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Programmer’s Model

3.4.1RTCPeriphID0 register

The RTCPeriphID0 register is hard-coded. The fields in the register determine the reset value. Table 3-11 shows the bit assignments for the RTCPeriphID0 register.

 

 

Table 3-11 RTCPeriphID0 register

 

 

 

Bits

Name

Description

 

 

 

15:8

-

Reserved. Read undefined. Must read as zeros.

 

 

 

7:0

PartNumber0

These bits read back as 0x31.

 

 

 

3.4.2RTCPeriphID1 register

The RTCPeriphID1 register is hard-coded. The fields in the register determine the reset value. Table 3-12 shows the bit assignments for the RTCPeriphID1 register.

 

 

Table 3-12 RTCPeriphID1 register

 

 

 

Bits

Name

Description

 

 

 

15:8

-

Reserved. Read undefined. Must read as zeros.

 

 

 

7:4

Designer0

These bits read back as 0x1.

 

 

 

3:0

PartNumber1

These bits read back as 0x0.

 

 

 

3.4.3RTCPeriphID2 register

The RTCPeriphID2 register is hard-coded. The fields in the register determine the reset value. Table 3-13 shows the bit assignments for the RTCPeriphID2 register.

 

 

Table 3-13 RTCPeriphID2 register

 

 

 

Bits

Name

Description

 

 

 

15:8

-

Reserved. Read undefined. Must read as zeros.

 

 

 

7:4

Revision

These bits read back as the revision number. This can

 

 

be between 0 and 15.

 

 

 

3:0

Designer1

These bits read back as 0x4.

 

 

 

ARM DDI 0224B

Copyright © 2001 ARM Limited. All rights reserved.

3-9

Programmer’s Model

3.4.4RTCPeriphID3 register

The RTCPeriphID3 register is hard-coded. The fields in the register determine the reset value. Table 3-14 shows the bit assignments for the RTCPeriphID3 register.

 

 

Table 3-14 RTCPeriphID3 register

 

 

 

Bits

Name

Description

 

 

 

15:8

-

Reserved. Read undefined. Must read as zeros.

 

 

 

7:0

Configuration

These bits read back as 0x00

 

 

 

3-10

Copyright © 2001 ARM Limited. All rights reserved.

ARM DDI 0224B

Programmer’s Model

3.5PrimeCell identification registers, RTCPCellID0-3

The RTCPCellID0-3 registers are four, 8-bit wide registers that span address locations 0xFF0 to 0xFFC. The registers can conceptually be treated as a 32-bit register, used as a standard cross-peripheral identification system. The RTCPCellID register is set to

0xB105F00D.

Figure 3-2 shows the bit assignments for the RTCPCellID0-3 registers.

Actual register bit assignment

RTCPCellID3

 

 

RTCPCellID2

 

RTCPCellID1

 

RTCPCellID0

7

0

7

0

7

0

7

0

31

24 23

16 15

8

7

0

RTCPCellID3

 

 

RTCPCellID2

 

RTCPCellID1

 

RTCPCellID0

Conceptual register bit assignment

Figure 3-2 PrimeCell identification register bit assignment

3.5.1RTCPCellID0 register

The RTCPCellID0 register is hard-coded. The fields in the register determine the reset value. Table 3-15 shows the bit assignments for the RTCPCellID0 register.

 

 

Table 3-15 RTCPCellID0 register

 

 

 

Bits

Name

Description

 

 

 

15:8

-

Reserved. Read undefined. Must read as zeros.

 

 

 

7:0

RTCPCellID0

These bits read back as 0x0D.

 

 

 

ARM DDI 0224B

Copyright © 2001 ARM Limited. All rights reserved.

3-11

Programmer’s Model

3.5.2RTCPCellID1 register

The RTCPCellID1 register is hard-coded. The fields in the register determine the reset value. Table 3-16 shows the bit assignments for the RTCPCellID1 register.

 

 

Table 3-16 RTCPCellID1 register

 

 

 

Bits

Name

Description

 

 

 

15:8

-

Reserved. Read undefined. Must read as zeros.

 

 

 

7:0

RTCPCellID1

These bits read back as 0xF0.

 

 

 

3.5.3RTCPCellID2 register

The RTCPCellID2 register is hard-coded. The fields in the register determine the reset value. Table 3-17 shows the bit assignments for the RTCPCellID2 register.

 

 

Table 3-17 RTCPCellID2 register

 

 

 

Bits

Name

Description

 

 

 

15:8

-

Reserved. Read undefined. Must read as zeros.

 

 

 

7:0

RTCPCellID2

These bits read back as 0x05.

 

 

 

3.5.4RTCPCellID3 register

The RTCPCellID3 register is hard-coded. The fields in the register determine the reset value. Table 3-18 shows the bit assignments for the RTCPCellID3 register.

 

 

Table 3-18 RTCPCellID3 register

 

 

 

Bits

Name

Description

 

 

 

15:8

-

Reserved. Read undefined. Must read as zeros.

 

 

 

7:0

RTCPCellID3

These bits read back as 0xB1.

 

 

 

3-12

Copyright © 2001 ARM Limited. All rights reserved.

ARM DDI 0224B