Programmer’s Model for Test
4.3Test registers
The PrimeCell RTC test registers are memory-mapped as shown in Table 4-1.
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Table 4-1 Test registers memory map |
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Address |
Type |
Width |
Reset value |
Name |
Description |
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RTC Base + 0x80 |
Read/write |
3 |
0x00000000 |
RTCITCR |
Integration test control register |
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RTC Base + 0x84 |
Read/write |
0 |
0x00000000 |
RTCITIP |
Integration test input read or set register |
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RTC Base + 0x88 |
Read/write |
1 |
0x00000000 |
RTCITOP |
Integration test output read or set |
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register |
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RTC Base + 0x8C |
Read/write |
32 |
0x00000000 |
RTCTOFFSET |
Test offset register |
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RTC Base + 0x90 |
Read/write |
32 |
0x00000000 |
RTCTCOUNT |
Test count register |
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Note
Test registers must not be accessed during normal operation.
4.3.1Integration test control register, RTCITCR
RTCITCR is the test control register. This general test register controls the operation of the PrimeCell RTC under test conditions. Table 4-2 shows the bit assignments for the RTCITCR register.
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Table 4-2 RTCITCR register |
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Bits |
Name |
Description |
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31:3 |
- |
Reserved. Unpredictable when read. Should be written as 0. |
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2 |
TESTOFFSET |
Test offset enable. When this bit is set to 1, data can be written |
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to and read from the offset register for test purposes. |
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When this bit is set to 0, data cannot be written to or read from |
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the offset register (normal operation). The reset value is 0. |
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1 |
TESTCOUNT |
Test count enable. When this bit is set to 1, data can be written |
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to and read from the counter register for test purposes. |
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When this bit is set to 0, data cannot be written to or read from |
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the counter register (normal operation). The reset value is 0. |
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0 |
ITEN |
Integration test enable. When this bit is 1, the RTC is placed |
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in integration test mode, otherwise it is in normal mode. |
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4-4 |
Copyright © 2001 ARM Limited. All rights reserved. |
ARM DDI 0224B |
Programmer’s Model for Test
4.3.2Integration test input read or set register, RTCITIP
RTCITIP is the integration test input read or set register. It is reserved for future use.
4.3.3Integration test output read or set register, RTCITOP
RTCITOP is the integration test output read or set register. The primary outputs are read only and the intra-chip outputs are read/write. In integration test mode it allows outputs to be both written to and read from. Table 4-3 shows the bit assignments for the RTCITOP register.
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Table 4-3 RTCITOP register |
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Bits |
Name |
Description |
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31:1 |
- |
Reserved. Unpredictable when read. |
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0 |
RTCINTR |
Intra-chip output. Writes specify the value to be driven on the |
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RTCINTR line in the integration test mode. Reads return the value of |
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the RTCINTR at the output of the test multiplexor. |
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4.3.4Test offset register, RTCTOFFSET
RTCTOFFSET is the test offset register. It allows data to be written into the offset register for test purposes. Table 4-4 shows the bit assignments for the RTCTOFFSET register.
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Table 4-4 RTCTOFFSET register |
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Bits |
Name |
Description |
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31:0 |
OFFSET |
Read/write register allowing reads and writes to the offset register for |
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test purposes. |
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4.3.5Test count register, RTCTCOUNT
RTCTCOUNT is the test count register. It allows data to be written into the counter register for test purposes. Table 4-5 shows the bit assignments for the RTCTCOUNT register.
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Table 4-5 RTCTCOUNT register |
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Bits |
Name |
Description |
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31:0 |
COUNT |
Read/write register allowing reads and writes to the counter register for |
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test purposes. |
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ARM DDI 0224B |
Copyright © 2001 ARM Limited. All rights reserved. |
4-5 |