Functional Overview

2.2PrimeCell GIR functional description

The PrimeCell GIR block diagram is shown in Figure 2-1.

Figure 2-1 PrimeCell GIR block diagram

2.2.1AMBA APB interface

The AMBA APB interface generates read and write decodes for accesses to status/ control registers and transmit/receive FIFO memories. The AMBA APB is a local secondary bus that provides a low-power extension to the higher bandwidth AMBA

Advanced High-performance Bus (AHB), or AMBA Advanced System Bus (AMBA

Functional Overview

ASB), within the AMBA system hierarchy. The AMBA APB groups narrow-bus peripherals to avoid loading the system bus and provides an interface using memorymapped registers, which are accessed under programmed control.

2.2.2Register block

The register block stores data written, or to be read across the AMBA APB interface.

2.2.3Receive and transmit clock divider

Transmit and receive clock enable signals are generated by dividing the input reference clock GIRCLK using programmed 16-bit values from the divide registers GIRTXGENCR and GIRRXGENCR. Each divider consists of a 16-bit down counter. The counter is loaded with the divide value when the transmit or receive functions are disabled, or when the counters reach zero.

2.2.4Transmit FIFO

The transmit FIFO is a 17-bit wide, 16-locations deep, first-in, first-out memory buffer. CPU data written across the AMBA APB interface are stored in the buffer until read out by the transmit logic.

2.2.5Receive FIFO

The receive FIFO is a 17-bit wide, 16-locations deep, first-in, first-out memory buffer. Received data from the serial interface are stored in the buffer until read out by the CPU across the AMBA APB interface.

2.2.6Transmit logic

The transmit logic generates pulses on GIROUT which have a defined logic level and duration according to the values written into the transmit FIFO. The logic level of the output pulse is set by one of the bits in the transmit FIFO data, and the remaining bits of the FIFO data are used for the reload value of a down counter. After the counter reaches zero, the logic level and duration of the output is again determined by the next transmit FIFO data. This process continues until all the data in the transmit FIFO have been sent as pulses. If modulation is enabled a HIGH logic level (1) is sent as a burst of carrier with a duty cycle as programmed in the register GIRTXDUTYCR. A LOW logic level (0) is represented as an absence of carrier.

Functional Overview

The main components of the transmit logic are:

•transmit state machine

•transmit timer

•carrier generation logic.

The transmit logic also provides status, FIFO interface and test signals.

2.2.7Receive logic

The receive logic processes and measures pulses representing a stream of digital symbols received at the GIRIN input and data are written to the receive FIFO.

The main components of the receive logic are:

•Input filter and synchronizer

•Demodulator

•Receive pulse timer.

Input filter and synchronizer

The filter rejects any signal which is shorter than a set threshold and the asynchronous signals are synchronized to the internal clock. The synchronized signals are then fed to a two-stage filter and edge detection logic uses the output of the filter to detect edges in the input data stream.

Demodulator

The demodulator retrieves the base-band signal from the filtered modulated input by:

•aligning itself to the rising edges in the input signal

•checking for three more valid edges

•making its output high for the same time as that of the input signal.

Receive pulse timer

The receive pulse timer measures the pulse width of the input pulses. The input to the pulse timer is the output of filter stage if the demodulator function is disabled, or else the output of the demodulator state machine is used. The timer is programmable to measure the pulse width between positive edges only, negative edges only, or between either rising or falling edges. In the demodulated case, the timer operates on both rising and falling edges. The end of transmission is signalled when the pulse timer overflows. When the pulse timer overflows, a time-out signal is set and the timer waits for an edge

Functional Overview

to appear on its input to start counting again. When an edge is detected on the input of the timer, the receive FIFO write signal is toggled to indicate that the data are ready to be written into the receive FIFO.

2.2.8Interrupt generation logic

Three individual maskable, active HIGH interrupts are generated by the PrimeCell GIR. A combined interrupt output is also generated as an OR function of the individual interrupt requests. The single combined interrupt may be used with a system interrupt controller that provides another level of masking on a per-peripheral basis. This allows use of modular device drivers which will always know where to find the interrupt source control register bits.

The individual interrupt requests could also be used with a system interrupt controller that provides masking for the outputs of each peripheral. In this way, a global interrupt controller service routine would be able to read the entire set of sources from one wide register in the system interrupt controller. This is attractive where the time to read from the peripheral registers is significant compared to the CPU clock speed in a real-time system.

The peripheral supports both the above methods, since the overhead is small. The transmit and receive data-flow interrupts, GIRTXINTR and GIRRXINTR, are separated from the status interrupts so that they can be used independently by a DMA controller. In this way, data can be read or written in response to just the FIFO trigger levels.

2.2.9Synchronizing registers and logic

The PrimeCell GIR supports both asynchronous and synchronous operation of the clocks, PCLK and GIRCLK. Synchronization registers and hand shaking logic have been implemented, and are active at all times. This has a minimal impact on performance and area. Synchronization of control signals is performed on both directions of data flow, that is from the PCLK to the GIRCLK domain and vice versa.

2.2.10Test registers and logic

There are registers and logic for functional block verification, and manufacturing or production test using TICTalk vectors.

Test registers should not be read or written to during normal use.

The test logic allows generation of a special test clock enable signal to propagate the test vectors applied to the input signal of the block, and to capture values at the block outputs.