Functional Overview

2.4PrimeCell GIR operation

PrimeCell GIR operation includes:

•Interface reset

•Clock signals

•Receive processing on page 2-12

•Receive demodulation on page 2-12

•Receive FIFO information on page 2-13

•Transmit processing on page 2-14

•Transmit modulation on page 2-14

•Clock dividers on page 2-16.

2.4.1Interface reset

The PrimeCell GIR is reset by the global reset signal BnRES and a PrimeCell GIRspecific reset signal nGIRRST. An external reset controller must use BnRES to assert nGIRRST asynchronously and negate it synchronously to GIRCLK. BnRES should be asserted LOW for a period long enough to reset the slowest block in the on-chip system, and then taken HIGH again. The PrimeCell GIR requires BnRES to be asserted for at least one period of PCLK and nGIRRST to be asserted for at least one period of

GIRCLK.

The values of the registers after reset are detailed in Chapter 3 Programmer’s Model.

2.4.2Clock signals

The PrimeCellGIR has two input clock signals, PCLK and GIRCLK.

The GIRCLK frequency value should be selected in acordance with the chosen method of operation. For further details refer to Clock dividers on page 2-16.

It is allowable to drive GIRCLK using the PCLK signal when the frequency value is suitable for the chosen method of operation, but often separate clock signals are required due to other system constraints.

However, there is a constraint on the ratio of frequencies for PCLK and GIRCLK.

FGIRCLK <= 20 x FPCLK

The frequency of GIRCLK must be less than 20 times the frequency of PCLK.

There is no restraint if the frequency of GIRCLK is less than the frequency of PCLK.

Functional Overview

2.4.3Receive processing

The received signal on GIRIN is a serial stream of digital symbols which may be modulated by a relatively high-frequency carrier signal (in the range 20-60 kHz). The overall purpose of the receive function is to measure the duration of these digital symbols, and present this information to the system for full decoding in software.

For situations where the received signal is modulated by a carrier signal, a programmable demodulator function is provided that recovers the digital data stream from the carrier. When the input signal does not contain a carrier, or has already been demodulated by external hardware, this function can be disabled. In either case, the input signal is first synchronized and squared up with respect to the local clock source, to improve the signal edge quality and reduce noise. The clean signal is then passed through an edge detection function, which detects edges in the data signal.

The receive logic uses an internal clock having a frequency which is a userprogrammable division of GIRCLK, the externally supplied clock. The frequency of the generated receive clock, must be set dependent on the expected symbol rate of the input. If the input is modulated by a carrier, the receive clock signal must be programmed to be 16 times the carrier frequency to allow successful demodulation.

The demodulated data (either direct from the input synchronization stage, or from the demodulator) is then applied to a timer/counter that measures the duration of symbols in integer multiples of the receive clock. This timer can be configured to measure the duration between each rising or falling edge (pulse period), or between the rising and falling edges (phase durations) in the data stream.

2.4.4Receive demodulation

When enabled, the demodulator is used to recover the baseband serial data from the carrier signal. The function works by aligning to a rising edge in the modulated signal and predicting when the next similar edge will arrive, within predefined window (limits defined by the winctrl bits within the GIRFCR control register). Because the receive clock must be 16 times the carrier frequency, the counter expects rising edges once every 16 clocks.

In addition, noise rejection is performed by checking for four consecutive occurrences of a valid input edge (where valid means that the edge arrives within the predefined window specified above). If these conditions are met, the input is considered valid and the demodulated output is produced. A similar noise rejection check is applied to detect the end of a burst of carrier pulses. The demodulator is therefore insensitive to a certain degree of noise and frequency inaccuracy. The output of the demodulator is delayed by four periods of the carrier frequency from the input. This should not affect the final decoding because the delay will be symmetrical between the start and end of the HIGH (modulated) symbols.

Functional Overview

2.4.5Receive FIFO information

The demodulated signal (either via the demodulator or directly from the input filter function) is then applied to a timer circuit which measures the duration of the symbols in the decoded signal.

The actual circuit is formed from a 20-bit timer/counter, clocked by the receive clock. When an edge is detected (marking the end of the current symbol), the 16 Most Significant Bits (MSBs) of this count are stored in the receive FIFO as a measure of symbol duration. Therefore, the duration of the symbol is derived from the value stored in the FIFO as follows:

Duration of Symbol = N x (1/FRX ) x 16

where FRX = Programmed receive clock rate

and N = Receive FIFO count value (bits [15:0] of GIRDATAR when read).

The maximum symbol duration which can be output is calculated as follows:

Tmax = (216 - 1) x (1/FRX) x 16

For example, with an expected carrier rate of 36kHz, the programmed receive clock would be set to (nominally) 576kHz, and the maximum measurable time is approximately 1.82 seconds. If there is no carrier to demodulate, the frequency of the receive clock can be set with more freedom.

A single bit representing the logic level of the most recently measured symbol, is stored in the FIFO at the same time as the counter value. On reading GIRDATAR, the 17 bits from the FIFO are appended with a further bit, RxDataAvail. This bit indicates whether there is further data in the FIFO after the current read.

When HIGH, RxDataAvail indicates that there is more data to be read from the FIFO. If RxDataAvail is LOW, it does not guarantee that the FIFO is empty. Thus a software routine wishing to empty the FIFO reads GIRDATAR until bit 17 is LOW, then reads from GIRSTAT to confirm that the FIFO is empty.

The end of the data transmission is detected when, following a data burst, the input becomes idle for so long that the duration timer reaches its 20-bit limit. This is reported via the FIFO as all bits set HIGH (1). This condition is used to report a timeout condition in the status register.

An interrupt output, GIRRXINT, is defined, which can be set to indicate either that the receive FIFO is half full or more, or that the FIFO is not empty.

The receive FIFO is 17 bits wide and 16 entries deep. The Data Available bit is generated instantaneously as a read occurs from GIRDATAR, and is not stored in the FIFO itself.

Functional Overview

2.4.6Transmit processing

The transmit logic generates pulses on GIROUT. The pulses have a defined logic level and duration according to the values written into the transmit FIFO, which is 17-bits wide and 16-entries deep.

The transmit data are encoded by software, and values are written to the transmit FIFO. Each value written uses one bit to determine the output logic level and the remaining bits are loaded into a counter to define the duration that the logic level is output.

When the transmit function is enabled, the counter decrements by one on each transmit clock. After the counter reaches zero, the logic level and duration of the output is again determined by the next transmit FIFO data. This process continues until all the data in the transmit FIFO has been sent as pulses. If modulation is enabled then a HIGH logic level 1 is sent as a burst of carrier with a duty cycle as programmed in the register GIRTXDUTYCR and a LOW logic level 0 is represented as an absence of carrier.

A transmit clock frequency is programmed using a 16-bit clock divider similar to that used in the receive portion. The frequency to be chosen is determined by the resolution and length of the output symbols required in a non-modulated mode. When modulation is required the frequency must be 16 times the carrier frequency.

When transmission is enabled and the FIFO contains data, the 16-bit value representing the required duration will be loaded into the MSB positions of a 20-bit counter similar to that used in the receive logic. The counter is allowed to decrement at the programmed transmit clock rate until it reaches zero. The next value is then loaded from the FIFO and the counter process restarts. End of transmission will be assumed when the present counter value reaches zero, and the transmit FIFO is empty. The output level will always return to a stable LOW level when transmission is completed.

The transmit interrupt output GIRTXINTR, can be programmed to indicate either that the transmit FIFO is less than, or equal to half-full (8 or less entries), or that the transmitter is not busy (disabled or transmission completed).

The duration of each symbol is:

Duration = N x (1/FTX ) x 16

where FTX = Programmed transmit clock rate

and N = Transmit FIFO count (bits [15:0] of GIRDATAR when written).

2.4.7Transmit modulation

If carrier generation is enabled, the data stream is modulated by the carrier such that marks, or HIGH periods will be replaced by carrier bursts of the same duration. Spaces in the output stream are represented by the absence of the carrier.

Functional Overview

The GIRTXDUTYCR register is used in the generation of the carrier signal, when the signal is enabled.

The register controls the duty cycle of the generated carrier signal.

The relationship between the register setting and the resulting carrier duty cycle is shown in Table 2-1.

Table 2-1 GIRTXDUTYCR register settings and resulting carrier duty cycle