- •9.7.2 More Timers And Counters
- •9.7.3 Deadman Switch
- •9.7.4 Conveyor
- •9.7.5 Accept/Reject Sorting
- •9.7.6 Shear Press
- •9.8 SUMMARY
- •9.9 PRACTICE PROBLEMS
- •9.10 PRACTICE PROBLEM SOLUTIONS
- •9.11 ASSIGNMENT PROBLEMS
- •10. STRUCTURED LOGIC DESIGN
- •10.1 INTRODUCTION
- •10.2 PROCESS SEQUENCE BITS
- •10.3 TIMING DIAGRAMS
- •10.4 DESIGN CASES
- •10.5 SUMMARY
- •10.6 PRACTICE PROBLEMS
- •10.7 PRACTICE PROBLEM SOLUTIONS
- •10.8 ASSIGNMENT PROBLEMS
- •11. FLOWCHART BASED DESIGN
- •11.1 INTRODUCTION
- •11.2 BLOCK LOGIC
- •11.3 SEQUENCE BITS
- •11.4 SUMMARY
- •11.5 PRACTICE PROBLEMS
- •11.6 PRACTICE PROBLEM SOLUTIONS
- •11.7 ASSIGNMENT PROBLEMS
- •12. STATE BASED DESIGN
- •12.1 INTRODUCTION
- •12.1.1 State Diagram Example
- •12.1.2 Conversion to Ladder Logic
- •12.1.2.1 - Block Logic Conversion
- •12.1.2.2 - State Equations
- •12.1.2.3 - State-Transition Equations
- •12.2 SUMMARY
- •12.3 PRACTICE PROBLEMS
- •12.4 PRACTICE PROBLEM SOLUTIONS
- •12.5 ASSIGNMENT PROBLEMS
- •13. NUMBERS AND DATA
- •13.1 INTRODUCTION
- •13.2 NUMERICAL VALUES
- •13.2.1 Binary
- •13.2.1.1 - Boolean Operations
- •13.2.1.2 - Binary Mathematics
- •13.2.2 Other Base Number Systems
- •13.2.3 BCD (Binary Coded Decimal)
- •13.3 DATA CHARACTERIZATION
- •13.3.1 ASCII (American Standard Code for Information Interchange)
- •13.3.2 Parity
- •13.3.3 Checksums
- •13.3.4 Gray Code
- •13.4 SUMMARY
- •13.5 PRACTICE PROBLEMS
- •13.6 PRACTICE PROBLEM SOLUTIONS
- •13.7 ASSIGNMENT PROBLEMS
- •14. PLC MEMORY
- •14.1 INTRODUCTION
- •14.2 MEMORY ADDRESSES
- •14.3 PROGRAM FILES
- •14.4 DATA FILES
- •14.4.1 User Bit Memory
- •14.4.2 Timer Counter Memory
- •14.4.3 PLC Status Bits (for PLC-5s and Micrologix)
- •14.4.4 User Function Control Memory
- •14.4.5 Integer Memory
- •14.4.6 Floating Point Memory
- •14.5 SUMMARY
- •14.6 PRACTICE PROBLEMS
- •14.7 PRACTICE PROBLEM SOLUTIONS
- •14.8 ASSIGNMENT PROBLEMS
- •15. LADDER LOGIC FUNCTIONS
- •15.1 INTRODUCTION
- •15.2 DATA HANDLING
- •15.2.1 Move Functions
- •15.2.2 Mathematical Functions
- •15.2.3 Conversions
- •15.2.4 Array Data Functions
- •15.2.4.1 - Statistics
- •15.2.4.2 - Block Operations
- •15.3 LOGICAL FUNCTIONS
- •15.3.1 Comparison of Values
- •15.3.2 Boolean Functions
- •15.4 DESIGN CASES
- •15.4.1 Simple Calculation
- •15.4.2 For-Next
- •15.4.3 Series Calculation
- •15.4.4 Flashing Lights
- •15.5 SUMMARY
- •15.6 PRACTICE PROBLEMS
- •15.7 PRACTICE PROBLEM SOLUTIONS
- •15.8 ASSIGNMENT PROBLEMS
plc design - 10.6
step4 bottom LS |
step2 |
step1
step1
FS
step1 |
flag up button |
step3 |
step2
step2
step2 |
top LS |
step4 |
step3
step3
step3 flag down button |
step1 |
step4
step4
step 1
down
motor
step 3
up motor
Figure 10.4 Process Sequence Bits Without Latches
10.3 TIMING DIAGRAMS
Timing diagrams can be valuable when designing ladder logic for processes that are only dependant on time. The timing diagram is drawn with clear start and stop times. Ladder logic is constructed with timers that are used to turn outputs on and off at appropriate times. The basic method is;
1. Understand the process.
plc design - 10.7
2.Identify the outputs that are time dependant.
3.Draw a timing diagram for the outputs.
4.Assign a timer for each time when an output turns on or off.
5.Write the ladder logic to examine the timer values and turn outputs on or off.
Consider the handicap door opener design in Figure 10.5 that begins with a verbal description. The verbal description is converted to a timing diagram, with t=0 being when the door open button is pushed. On the timing diagram the critical times are 2s, 10s, 14s. The ladder logic is constructed in a careful order. The first item is the latch to seal-in the open button, but shut off after the last door closes. auto is used to turn on the three timers for the critical times. The logic for opening the doors is then written to use the timers.
plc design - 10.8
Description: A handicap door opener has a button that will open two doors. When the button is pushed (momentarily) the first door will start to open immediately, the second door will start to open 2 seconds later. The first door power will stay open for a total of 10 seconds, and the second door power will stay on for 14 seconds. Use a timing diagram to design the ladder logic.
Timing Diagram:
door 1
door 2
2s |
10s |
14s |
Ladder Logic:
open button |
T4:2/DN |
auto
auto
auto
TON Timer T4:0 Delay 2s
TON
Timer T4:1
Delay 10s
TON
Timer T4:2
Delay 14s
T4:1/TT
door 1
T4:2/TT T4:0/DN
door 2
Figure 10.5 Design With a Timing Diagram
plc design - 10.9
10.4DESIGN CASES
10.5SUMMARY
•Timing diagrams can show how a system changes over time.
•Process sequence bits can be used to design a process that changes over time.
•Timing diagrams can be used for systems with a time driven performance.
10.6PRACTICE PROBLEMS
1.Write ladder logic that will give the following timing diagram for B after input A is pushed. After A is pushed any changes in the state of A will be ignored.
true |
|
|
|
|
|
false |
|
|
|
|
t(sec) |
0 |
2 |
5 |
6 |
8 |
9 |
2.Design ladder logic for the timing diagram below. When an input A becomes active the sequence should start.
X
Y |
Z
t (ms)
100 |
300 |
500 |
700 |
900 |
1100 |
1900 |
3.A wrapping process is to be controlled with a PLC. The general sequence of operations is described below. Develop the ladder logic using process sequence bits.
1.The folder is idle until a part arrives.
2.When a part arrives it triggers the part sensor and the part is held in place by actuating the hold actuator.