- •9.7.2 More Timers And Counters
- •9.7.3 Deadman Switch
- •9.7.4 Conveyor
- •9.7.5 Accept/Reject Sorting
- •9.7.6 Shear Press
- •9.8 SUMMARY
- •9.9 PRACTICE PROBLEMS
- •9.10 PRACTICE PROBLEM SOLUTIONS
- •9.11 ASSIGNMENT PROBLEMS
- •10. STRUCTURED LOGIC DESIGN
- •10.1 INTRODUCTION
- •10.2 PROCESS SEQUENCE BITS
- •10.3 TIMING DIAGRAMS
- •10.4 DESIGN CASES
- •10.5 SUMMARY
- •10.6 PRACTICE PROBLEMS
- •10.7 PRACTICE PROBLEM SOLUTIONS
- •10.8 ASSIGNMENT PROBLEMS
- •11. FLOWCHART BASED DESIGN
- •11.1 INTRODUCTION
- •11.2 BLOCK LOGIC
- •11.3 SEQUENCE BITS
- •11.4 SUMMARY
- •11.5 PRACTICE PROBLEMS
- •11.6 PRACTICE PROBLEM SOLUTIONS
- •11.7 ASSIGNMENT PROBLEMS
- •12. STATE BASED DESIGN
- •12.1 INTRODUCTION
- •12.1.1 State Diagram Example
- •12.1.2 Conversion to Ladder Logic
- •12.1.2.1 - Block Logic Conversion
- •12.1.2.2 - State Equations
- •12.1.2.3 - State-Transition Equations
- •12.2 SUMMARY
- •12.3 PRACTICE PROBLEMS
- •12.4 PRACTICE PROBLEM SOLUTIONS
- •12.5 ASSIGNMENT PROBLEMS
- •13. NUMBERS AND DATA
- •13.1 INTRODUCTION
- •13.2 NUMERICAL VALUES
- •13.2.1 Binary
- •13.2.1.1 - Boolean Operations
- •13.2.1.2 - Binary Mathematics
- •13.2.2 Other Base Number Systems
- •13.2.3 BCD (Binary Coded Decimal)
- •13.3 DATA CHARACTERIZATION
- •13.3.1 ASCII (American Standard Code for Information Interchange)
- •13.3.2 Parity
- •13.3.3 Checksums
- •13.3.4 Gray Code
- •13.4 SUMMARY
- •13.5 PRACTICE PROBLEMS
- •13.6 PRACTICE PROBLEM SOLUTIONS
- •13.7 ASSIGNMENT PROBLEMS
- •14. PLC MEMORY
- •14.1 INTRODUCTION
- •14.2 MEMORY ADDRESSES
- •14.3 PROGRAM FILES
- •14.4 DATA FILES
- •14.4.1 User Bit Memory
- •14.4.2 Timer Counter Memory
- •14.4.3 PLC Status Bits (for PLC-5s and Micrologix)
- •14.4.4 User Function Control Memory
- •14.4.5 Integer Memory
- •14.4.6 Floating Point Memory
- •14.5 SUMMARY
- •14.6 PRACTICE PROBLEMS
- •14.7 PRACTICE PROBLEM SOLUTIONS
- •14.8 ASSIGNMENT PROBLEMS
- •15. LADDER LOGIC FUNCTIONS
- •15.1 INTRODUCTION
- •15.2 DATA HANDLING
- •15.2.1 Move Functions
- •15.2.2 Mathematical Functions
- •15.2.3 Conversions
- •15.2.4 Array Data Functions
- •15.2.4.1 - Statistics
- •15.2.4.2 - Block Operations
- •15.3 LOGICAL FUNCTIONS
- •15.3.1 Comparison of Values
- •15.3.2 Boolean Functions
- •15.4 DESIGN CASES
- •15.4.1 Simple Calculation
- •15.4.2 For-Next
- •15.4.3 Series Calculation
- •15.4.4 Flashing Lights
- •15.5 SUMMARY
- •15.6 PRACTICE PROBLEMS
- •15.7 PRACTICE PROBLEM SOLUTIONS
- •15.8 ASSIGNMENT PROBLEMS
plc timers - 9.32
9.10 PRACTICE PROBLEM SOLUTIONS
1.edge triggered means the event when a logic signal goes from false to true (positive edge) or from true to false (negative edge).
4.no, but they are essential for retentive timers, and very important for counters.
5.these are limited by the 16 bit number for a range of -32768 to +32767
6.the un underflow bit. This may result in a fault in some PLCs.
7.
first pass
U motor
stop
start
L motor
start |
stop |
motor
motor
8.
input |
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TON |
delays turning on |
TOF |
delays turning off |
plc timers - 9.33
9.
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RTF |
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A |
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Timer T4:0 |
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Time Base 0.01 |
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Preset 350 |
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Accum. 0 |
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A |
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T4:0/EN |
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T4:0/DN |
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T4:0/TT |
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T4:0.Accum. |
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0 |
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6 |
10 |
16 |
18 |
20 |
plc timers - 9.34
10.
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RTO |
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Timer T4:0 |
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Time Base 1.0 |
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Preset 10 |
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Accum. 1 |
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A |
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T4:0 EN |
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T4:0 TT |
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T4:0 DN |
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T4:0 Accum. |
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6 |
9 |
14 |
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19 |
20 |
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TOF |
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A |
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Timer T4:1 |
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Time Base .01 |
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Preset 50 |
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Accum. 0 |
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A |
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T4:1 EN |
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T4:1 TT |
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T4:1 DN |
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T4:1 Accum. |
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0 |
15 |
45 |
150 |
200 |
225 |
plc timers - 9.35
11.
input
TON
RTO
TOF
RTF
sec
0 |
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2 |
3 |
4 |
5 |
6 |
7 |
12.
A |
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RTO |
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Timer T4:0 |
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Base 1.0 |
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Preset 2 |
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A |
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RES T4:0 |
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13.
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A |
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T4:0/DN |
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Timer T4:0 |
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Base 1.0 |
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Preset 3600 |
T4:0/DN |
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CTU |
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Counter C5:0 |
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Preset 1200 |
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C5:0/DN
Light
plc timers - 9.36
14.
I/1
B3/0
B3/0
T4:0/DN
15.
I/2
I/1
C5:0/DN
B3/0
TON
T4:0
delay 15 sec
O/01
C5:0 RES
CTU
C5:0 presetR 10
O/1
plc timers - 9.37
16.
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I/1 |
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T4:1/DN |
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T4:0/DN
T4:0/DN
T4:1/DN
C5:0/DN
TON
T4:0 delay 20 s
TON
T4:1 delay 20 s
O/1
L
CTU
C5:0 preset 3
O/1
U
plc timers - 9.38
17.
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go |
stop |
C5:0/DN |
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C5:1/DN |
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go |
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CTU |
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Counter C5:0 |
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Preset 2 |
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Accumulator 1 |
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CTU |
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Counter C5:1 |
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Preset 3 |
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Accumulator 1 |
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C5:1/DN |
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RES |
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C5:0 |
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RES |
C5:1 |
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stop |
C5:0/DN |
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CTD |
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Counter C5:0 |
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Preset 2 |
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Accumulator 1 |
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CTD |
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Counter C5:1 |
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Preset 3 |
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Accumulator 1 |
plc timers - 9.39
18.
left button |
TON |
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Timer T4:0 |
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Base 0.01 |
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Preset 25 |
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right button |
TON |
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Timer T4:1 |
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Base 0.01 |
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Preset 25 |
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T4:0/TT |
T4:1/TT |
stop |
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on |
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on |
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plc timers - 9.40
19.
S1
CTU
Counter C5:0
Preset 6
CTU
Counter C5:1
Preset 1
S2
CTD
Counter C5:0
Preset 6
CTD
Counter C5:1
Preset 1
C5:0/DN
C1
C5:1/DN
C2
C5:0/DN
TON
Timer T4:0
Preset 30s
T4:0/DN
RES C5:0
RES C5:1
plc timers - 9.41
20.
A |
C5:0/DN |
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TON |
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timer T4:0 |
T4:0/TT |
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delay 5s |
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T4:0/TT |
T4:2/DN |
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TON |
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timer T4:1 |
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delay 0.25s |
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T4:1/DN |
TON |
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timer T4:2 |
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delay 0.75s |
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CTU |
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counter C5:0 |
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preset 5 |
T4:1/TT |
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light |
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B |
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RES |
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plc timers - 9.42
21.
First scan
TON
T4:0
delay 15s
T4:0/TT
T4:2/DN
TON T4:1 delay 0.5s
T4:1/DN
TON
T4:2 delay 0.5s
T4:0/TT |
light |
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22.
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start |
stop |
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active |
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active |
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enter |
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CTU |
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counter C5:0 |
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preset 10 |
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exit |
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CTD |
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counter C5:0 |
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preset 10 |
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C5:0/DN |
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active |
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23. The normal output ‘Y’ is repeated twice. In this example the value of ‘Y’ would always match ‘B’, and the earlier rung with ‘A’ would have no effect on ‘Y’.