This macro generates the minimum number of instructions needed to do the job. There is no loop overhead, prolog or epilog in the final code. And, most importantly, no branches. All branches have been resolved by the macro preprocessor. To calculate XMM0 to the power of 12, you write:

INTPOWER XMM0, XMM1, 12

This will be resolved to:

This even has fewer instructions than the optimized loop (example 16.13). The expanded macro takes 25 clock cycles in this example.

17 Single-Instruction-Multiple-Data programming

Since there are technological limits to the maximum clock frequency of microprocessors, the trend goes towards increasing processor throughput by handling multiple data in parallel.

When optimizing code, it is important to consider if there are data that can be handled in parallel. The principle of Single-Instruction-Multiple-Data (SIMD) programming is that a vector or set of data are packed together in one large register and handled together in one operation.

Multiple data can be packed into 64-bit or 128-bit registers in the following ways:

;register use:

;XMM0 = xp

;XMM1 = power

; XMM2 = i (i0 and i1 each stored twice as DWORD integers)

;XMM3 = 1.0 if not(i & 1)

;XMM4 = xp if (i & 1)

Conditional moves in SIMD registers are implemented by generating a mask of all 1's representing the condition; AND'ing the first operand with the mask; AND'ing the second operand with the inverted mask; and OR'ing the two together. The mask can be generated by a compare instruction or, as here, by shifting a bit into the most significant position and then shifting it arithmetically to copy it into all positions. The arithmetic shift does not exist in a 64-bit version, so we have to use the 32-bit version with two identical copies of the condition operand.

The repeat count of the loop is calculated separately outside the loop in order to reduce the number of instructions inside the loop.

Timing analysis for example 17.1 in P4: There are four continued dependence chains: XMM0: 6 clocks, XMM1: 6 clocks, XMM2: 2 clocks, ECX: ½ clock. Throughput for the different execution units: MMX-SHIFT: 3 uops, 6 clocks. MMX-ALU: 3 uops, 6 clocks. FP-MUL: 2 uops, 4 clocks. Throughput for port 1: 8 uops, 8 clocks. Thus, the loop appears to be limited by port 1 throughput. The best timing we can hope for is 8 clocks per iteration which is the number of uops that must go to port 1. However, three of the continued dependence chains are interconnected by two broken, but quite long, dependence chains involving XMM3 and XMM4, which take 22 and 18 clocks, respectively. This tends to hinder the optimal reordering of uops. The measured time is approximately 10 uops per iteration. This timing actually requires a quite impressive reordering capability, considering that several iterations must be overlapped and several dependence chains interwoven in order to satisfy the restrictions on all ports and execution units.

In situations like this where it is difficult to obtain the optimal reordering of uops, it may require some experimentation to find the optimal solution. By experimentation I found that the code in example 17.1 can be made approximately 16 clocks faster in total by modifying it to the following:

Here I have used PXOR and PANDN, rather than XORPD and ANDNPD, where the result of the operation may not be a valid floating-point number.

These examples shows that conditional moves in SIMD registers are quite complicated and involve considerable dependence chains. However, conditional moves are unavoidable in SIMD programming if the conditions are not the same for all operands in a pack. In the above example, the conditional moves can only be replaced by branches if n0 and n1 have the same value.

Conditional moves in 32-bit registers are no faster than in SIMD registers. The reason why conditional moves are so complex and inefficient is that they have three dependencies, while the hardware design does not allow any uop to have more than two dependencies.

Packing operands in 32-bit registers

Sometimes it is possible to handle packed data in 32-bit registers. You may use this method to take advantage of the fact that 32-bit operations are fast, or to make the code compatible with old microprocessors.

A 32-bit register can hold two 16-bit integers, four 8-bit integers, or 32 Booleans. When doing calculations on packed integers in 32-bit registers, you have to take special care to avoid carries from one operand going into the next operand if overflow is possible. The following example adds 2 to all four bytes in EAX: