Embedded system engineering magazine 2005.06

THERE ARE significant developments in Multi-Media and High Definition Television, in both hardware and software. New high performance processors, wireless communi-

cation links and networks are impacting on the design of new products. Microsoft has recently released Version 5.0 of its Windows Mobile product which includes increased platform flexibility allowing developers to plug in differentiated technologies such as "push-to-talk" or video calling and conferencing. There is also support for higher-band- width 3G networks, Wi-Fi for the Smartphone platform and improvements to existing Bluetooth support, enabling more flexibility to integrate mobile phone services across a variety of networks. Microsoft has also released Windows Media Player 10 Mobile which allows customers to control a larger number of protected digital music, video and

inch LCD TV, show that the home entertainment revolution continues apace. There will soon be a merger between the functions of the PC, the smart phone and the TV. Why should a user be restricted to a 2inch or even a 17inch screen when they can have a much larger one in their living room. The technology behind the HDTV expansion is highly integrated and there are some very powerful specialised processors being used.

Not so long ago Zoran Corporation announced that it had integrated the capabilities of five separate components into a new SupraHD family of high definition television processors including the video decoder, HDMI receiver, 1394, audio DAC, and an advanced video processing engine to control and directly drive LCD and other high definition television

platform provides extensive advanced compression codec support including H.264/AVC, Windows Media 9, VC-1, and MPEG -2. This will allow operators to deliver hundreds of television channels, digital audio, web browsing, gaming and e-mail directly into the living room over existing DSL lines.

New processors target video

Perhaps one of the most dramatic new architectures to be announced in recent times has been the CELL processor, jointly developed by Sony, Toshiba and IBM, see a detailed description in the box out on page 34.

Other processor developments

The Blackfin Processor family from Analog Devices has been expanded to include three

recorded television files. These can be synchronized easily from a PC or downloaded from many Internetbased services and mobile operators' music stores with Windows Media Player 10 Mobile.

Video on phones

PacketVideo has recently demonstrated a mobile media application playing Microsoft Windows Media audio and video on Nokia Series 60 phones. PacketVideo's featured demonstration closely followed the announcement made by Nokia and Microsoft outlining collaboration on digital media formats, including support for Windows Media Audio and Media Transfer Protocol (MTP) on music-oriented Nokia handsets, plus support for the MPEG Advanced Audio Coding (AAC) family of codecs. PacketVideo has demonstrated both Windows Media Audio, and Windows Media Video on Nokia 6680 and 6630 phones.

Not just TV anymore

The recent demonstration by LG Electronics of a 71 inch plasma TV (decorated in gold!) and a 50

displays. Developments like this greatly reduce the overall system cost for manufacturers of digital televisions as well as improving reliability.

The first two members of the SupraHD family, SHD-660 and SHD-680 combine traditional digital functions and highly integrated connectivity with advanced capabilities for analogue video capture and display. These single-chip solutions contain an advanced video processing engine to control and drive LCDs, rear and front projection, and plaza displays. The SHD-660 (ZR39660) includes a digital terrestrial reception, ATSC compliant HDTV decoder and, the SHD680 (ZR39680) adds further support for Unidirectional Digital Cable (UDC) and a CableCard interface.

Thomson recently announced that it is expanding its IPTV product portfolio with the introduction of the IP1100 High Definition Networked Entertainment Set-Top Box Platform. This is designed to enable telephone and IPTV service operators to deliver affordable standard and high-definition video content. The IP1100

new devices providing a wide range of performance and price points. They are marketed on the back of their signal and control processing performance, enhanced Dynamic Power Management, and application-tuned peripherals designed to simplify the development of a wide range of applications, including embedded video. The family members are completely code and pin compatible, mitigating the design risks associated with new product developments. System designers can maximize algorithm reuse and provide software-differentiated end products without the need for hardware redesign.

The ADSP-BF533 is the highest performance series member and is well suited for embedded video applications such as consumer video, security/surveillance, and broadband home gateways. The ADSP-BF532 also offers exceptional performance, but with a reduced memory, which balances performance with cost in applications such as automotive telematics and information appliances. The ADSP-BF531 is the low cost entry point into the >>

The idea of throwing multiple processors at a problem is not by any means new. The problems in the past have been costs, due to the lack of volume demand; poor interprocessor communication rates and little or no acceptable software tools. Now Sony, Toshiba and IBM have come up with the CELL processor. The first iteration uses a PowerPC core and 8 slave DSP type processors, operating as a Single Instruction Multiple Data (SIMD) machine. It will be used in the long awaited PS3 and in Toshiba digital televisions from 2006. Applications where multiply threaded DSP operations prevail will be the ones to benefit from this technology. Not just imaging per se but acoustics, ballistics, in fact anything that needs matrix computation could be considered as a potential application.

Members of the CELL processor family share basic building blocks, and depending on the requirement of the application, specific versions of the CELL processor can be quickly configured and manufactured to meet that need. The basic building blocks shared by members of the CELL family of processor are the following:

●The PowerPC Processing Element (PPE)

●The Synergistic Processing Element (SPE)

●The L2 Cache

●The internal Element Interconnect Bus(EIB)

●The shared Memory Interface Controller (MIC) and

●The FlexIO interface

Each SPE is in essence a private system-on- chip (SoC), with the processing unit connected directly to 256KB of private Load Store (LS) memory. The PPE is a dual threaded PowerPC processor connected to the SPE's through the EIB. The PPE and SPE processing elements access system memory through the MIC, which is connected to two independent channels of Rambus XDR memory, providing 25 GB/s of memory bandwidth. The connection to I/O is done through the FlexIO interface, also provided by Rambus, providing 44.8 GB/s of raw outbound BW and 32 GB/s of raw inbound bandwidth for total I/O band-

Samsung Electronics. Already systems have been demonstrated that can transmit two HDTV channels simultaneously(Mitsubishi) and can down load an image from a phone to a PC in a second (Samsung/Freescale)

Freescale's XS110 Ultra-Wideband (UWB) solution provides wireless connectivity by implementing direct sequence ultra-wideband (DS-

width of 76.8 GB/s. In the CELL processor, each SPE is capable of sustaining 4 FMADD operations per cycle. At an operating frequency of 4 GHz, the CELL processor is thus capable of achieving a peak throughput rate of 256 GFlops from the 8 SPE's. Moreover, the PPE can contribute some amount of additional compute power with its own FP and VMX units.

In the CELL processor, the software manages the DMA and reserves channels to move data to and from the LS. The DMA is programmed and resources allocated for the movement of data in response to requests. The request queue in the SPE supports up to 16 outstanding requests. Each request can transfer up to 16 Kb of data. Once the data is moved into the LS, the SPE then performs the computation by accessing the private LS in isolation. Ideally, each SPE would overlap computation with data streaming, and two or more software managed threads can operate concurrently on a SPE at a given instance in time. In such a scenario, while one thread is moving data in and out of the LS via the DMA engine, a second thread can occupy the computing resources of the SPE.

One interesting aspect of the floating point pipeline is that the same arrays are used for floating point computation as well as integer multiplication. As a result, integer multiplies are sent to the floating point pipeline, and the floating point pipeline bypasses the FP handling and computes the integer multiply. The element interconnect bus is the on chip interconnect that ties together all of the processing, memory, and I/O elements on the CELL processor. The EIB is implemented as a set of four concentric rings that is routed through portions of the SPE, where each ring is a 128 bit wide interconnect.

THE SOFTWARE: The nature of the software tools, the operating systems and compilers, has yet to be revealed but one thing is for sure, unless the development process is supported with effective tools and means of porting existing games to the PS3, the innovative hardware technology might not be enough for the product to survive.

UWB) and the IEEE 802.15.3 media access control (MAC) protocol. The chipset delivers more than 110 Mbps data transfer rate supporting applications such as streaming video, streaming audio, and high-rate data transfer at very low levels of power consumption. In addition to high data rates, the XS110 supports peer-to-peer as well as ad hoc networking. <Ends>

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WITH EVER-INCREASING speeds of system CPUs, overall system performance is now often limited by I/O bandwidth, i.e. the ability to move data in,

out, and between boards and systems. This has resulted in traditional parallel bus structures, like those used in CompactPCI and VME, running up against limits imposed by physics.

Since most complex computer architecture has many sources and destinations for data, it follows that a backplane, which provides multiple paths to link those sources and destinations, will be quicker than one which relies on a limited number of fixed links. Thus there has recently been a move away from the traditional bus based structure for the backplane and utilisation of a star or mesh configuration.

In a switched fabric, the electrical capacitance of the data link is reduced to a minimum by having only one source and destination at

any point in time. This permits higher speed operation than would be possible with a conventional multi-drop parallel bus; wherein each board plugged into the bus adds capacitance and thus limits the speed. A simple visualisation is that of the horizontal and vertical threads of a piece of cloth, with the crossover points being the switch element. Hence the term “switched fabric”.

Fabric agnostic

To ensure universal acceptance, PICMG have approached “Advanced Telecommunication Computing Architecture” (AdvancedTCA) as a “fabric agnostic” platform such that any of the emerging switched fabrics may be used to drive a “standard” system. The core standard defines mechanical structure; power distribution, cooling, system management, and the data fabric interconnect including connectors. AdvancedTCA

is an open industry standard with no royalties or license for use, and is covered by a series of specifications, under the generic PICMG 3.X. Currently the following have been adopted: PICMG3.0 Serial Interconnect; PICMG3.1 Ethernet; PICMG3.2 InfiniBand; PICMG3.3 Star Fabric; and PICMG3.4 PCI Express.

The AdvancedTCA switched fabric provides “full mesh” interconnectivity between boards. With a full mesh architecture, each board connects simultaneously to every other board. In a sixteen slot system, this means that higher speed links are provided on the backplane so that every board has a direct connection to the other fifteen boards in the system. Overall infrastructures like system management and power distribution are also provided on the backplanes.

For a lower cost backplane solution some system builders are looking at dual-star for full redundancy. This provides links from 2 fabric

slots to each peripheral point (node) on the backplane. With the dual-dual-star configuration an additional pair of fabric slots is included to improve bandwidth. Both of these configurations require less layers in the backplane and thus reduce the cost when compared to the full mesh structure.

Board based

An AdvancedTCA platform looks a lot like a conventional board-based sys-

tem and the mechanics used are mainly based upon the same IEC60297 standard found in VME and CompactPCI. While AdvancedTCA uses a backplane and plug-in

boards, the similarity to >>

PICMG and AdvancedTCA

PICMG (PCI Industrial Computer Manufacturers Group) is a consortium of over 450 companies, founded in 1994, who collaboratively develop open specifications for high performance telecommunications and industrial computing applications. The members of the consortium have a long history of developing leading edge products for these industries. PICMG specifications include CompactPCI for Eurocard, rackmount applica-

tions and PCI/ISA for passive backplane, standard format cards.

PICMG's purpose is to offer equipment vendors common specifications, thereby increasing availability and reducing costs and time to market. The PCI specifications provide a clear upgrade path for OEMs wishing to migrate to new designs.

Recently, PICMG announced it was begin-

ning development of a new series of specifications, called AdvancedTCA, for next-genera- tion telecommunications equipment, with a new form factor and based on switched fabric architectures.

This is the largest specification effort in PICMG's history, with more than 100 companies participating. It incorporates the latest trends in high speed interconnect technologies, next generation processors and

improved reliability, manageability and serviceability.

Companies participating in the AdvancedTCA effort have brought a wide range of knowledge of the industry. They include telecommunications equipment manufacturers, board and system level vendors, computer OEMs, software companies and chassis, connector and power supply vendors.

Rittal has investigated thermal design in order to provide adequate chassis cooling, as each board in an AdvancedTCA system may generate up to 200 watts of heat. (400Watts is already being discussed, for which alternative forms of cooling will almost certainly be necessary).

Using Computational Fluid Dynamics (CFD) it has been demonstrated that adequate forced air-cooling can be provided, with correct system design, even in the event of a single fan failure. This allows a 10 degree C temperature rise in cooling air, from air ingress to exhaust, based on 55 degree Celsius ambient. For future higher power consumption systems, it may be necessary to separately cool the individual components that generate the greatest heat.

Distributed power

The high power capability of the AdvancedTCA platform caused a re-think of the way power is distributed to boards and around the system. Distributing low voltages such as 3.3V at hundreds of amperes of current over a backplane does not make sense, especially when modern microprocessor core logic voltages are a volt or so and require local DC-DC converters anyway.

Distributing a higher voltage at a lower current and providing dual feeds for redundancy makes more sense, hence the AdvancedTCA system uses on-board DC-DC power conversion as a standard.

One important issue often overlooked in system design is I/O cabling and its maintenance. High-end platforms like AdvancedTCA require a wide variety and lots of I/O connectivity, including high-speed network, fibre optic and high-density connections. One approach to I/O cabling, pioneered by Rittal, involves transition modules at the rear of the chassis, with each module passing I/O to the main front plug-in board via connectors. While in VME and CompactPCI systems these connections pass through the backplane, with AdvancedTCA the rear transition is set to become a matched unit with the front plug-in card. This improves the up-grade ability of the plug-in board due to the rear transition module having a direct connection and by-passing