Forth Programmer’s Handbook

References PAD, Section 2.3.1

Terminal I/O, Section 3.3

Interrupts, Section 5.11

1.3 THE FORTH ASSEMBLER

Most Forth systems contain an assembler for the CPU on which the system runs. Although it offers most of the same capabilities of other assemblers, its integration into the Forth environment means it may not be fully compatible with assemblers supplied by the computer’s manufacturer.

A Forth assembler produces exactly the same code as a conventional assembler (which means it runs at full machine speed), but does it somewhat differently. The differences are in notation and procedure, and are described in the following sections.

1.3.1 Notational Differences

Notational differences occur for two reasons:

!To improve transportability of Forth applications between processors by making assembler notation as similar as possible, without impairing the programmer’s ability to access and control the processor fully; and

!To yield a compact assembler which can be resident at all times, to facilitate interactive programming and debugging.

This section describes some typical practices.

1.3.1.1 Instruction Mnemonics

Most Forth assembler mnemonics that specify assembler instructions are the same as the manufacturer’s mnemonics. Occasionally, there are differences if the manufacturer uses a prefix or suffix on the mnemonic to describe something Forth specifies as a parameter or to differentiate instructions which are really different. For example, Motorola’s 68xxx ADD instruction may be one of four variants; one popular Forth 68xxx cross-assembler uses one ADD instruc-

Introduction 19

Forth Programmer’s Handbook

tion modified by its parameters. Intel uses MOV for both memory/register operations and segment register operations in the 80x86 family, whereas some Forth assemblers have different instruction names when segment registers are involved, because the internal instruction format is quite different. The net effect of these differences is usually to facilitate keeping the assembler resident at all times, without adverse impact even on relatively limited platforms, leading in turn to significantly simplified development procedures.

1.3.1.2 Addressing Modes

In all computing, there are only a few specific addressing modes (register direct, register relative, memory indirect, etc.). Notation specifying these has been standardized across all Forths, to make it easier for programmers working with several different CPUs. Naturally, this means the notation differs from the manufacturer’s notation; however, all modes supported by the processor are implemented in the Forth assembler.

1.3.1.3 Instruction Format

Most assemblers encourage a four-column format, with one instruction per line, allowing space for labels, opcodes, addressing operands, and remarks. In Forth, the opcode itself is a Forth command which assembles the instruction according to addressing operands passed on the stack. This leads to a format in which the addressing mode specifiers precede the opcode.

1.3.1.4 Labels, Branches, and Structures

Forth assemblers support structured programming in the same way high-level Forth does. Arbitrary branching to labelled locations is discouraged; on the other hand, structures such as BEGIN … UNTIL and IF … ELSE … THEN are available in the assembler, implemented as macros that assemble appropriate conditional and unconditional branches.

20 Introduction