3.3Summary of PrimeCell DMA controller registers

The PrimeCell DMA controller registers are shown in Table 3-1.

Table 3-1 PrimeCell DMA controller register summary

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

DMA controller	Read	8	0x00	DMACIntStatus	This register provides the
base + 0x000					interrupt status of the
					PrimeCell DMA controller. A
					HIGH bit indicates that a
					specific DMA channel
					interrupt is active.

DMA controller	Read	8	0x00	DMACIntTCStatus	This register is used to
base + 0x004					determine whether an interrupt
					was generated due to the
					transaction completing
					(terminal count). A HIGH bit
					indicates that the transaction
					completed.

DMA controller	Write	8	-	DMACIntTCClear	When writing to this register,
base + 0x008					each data bit that is HIGH
					causes the corresponding bit in
					the DMACIntTCStatus and
					DMACRawIntTCStatus
					registers to be cleared. Data
					bits that are LOW have no
					effect on the corresponding bit
					in the register.

DMA controller	Read	8	0x00	DMACIntErrorStatus	This register is used to
base + 0x00C					determine whether an interrupt
					was generated due to an error
					being generated.

DMA controller	Write	8	-	DMACIntErrClr	When writing to this register,
base + 0x010					each data bit that is HIGH
					causes the corresponding bit in
					the DMACIntErrorStatus and
					DMACRawIntErrorStatus
					registers to be cleared. Data
					bits that are LOW have no
					effect on the corresponding bit
					in the register.

3-6		Copyright © 2000, 2001 ARM Limited. All rights reserved.			ARM DDI 0196C

					Programmer’s Model
			Table 3-1 PrimeCell DMA controller register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

DMA controller	Read	8	-	DMACRawIntTCStatus	This register provides the raw
base + 0x014					status of DMA terminal count
					interrupts prior to masking. A
					HIGH bit indicates that the
					interrupt request is active prior
					to masking.

DMA controller	Read	8	-	DMACRawIntErrorStatus	This register provides the raw
base + 0x018					status of DMA error interrupts
					prior to masking. A HIGH bit
					indicates that the interrupt
					request is active prior to
					masking.

DMA controller	Read	8	0x00	DMACEnbldChns	This register shows which
base + 0x01C					DMA channels are enabled. A
					HIGH bit indicates that a DMA
					channel is enabled.

DMA controller	Read/write	16	0x0000	DMACSoftBReq	This register allows DMA
base + 0x020					burst requests to be generated
					by software.

DMA controller	Read/write	16	0x0000	DMACSoftSReq	This register allows DMA
base + 0x024					single requests to be generated
					by software.

DMA controller	Read/write	16	0x0000	DMACSoftLBReq	This register allows DMA last
base + 0x028					burst requests to be generated
					by software.

DMA controller	Read/write	16	0x0000	DMACSoftLSReq	This register allows DMA last
base + 0x02C					single requests to be generated
					by software.

DMA controller	Read/write	3	0b000	DMACConfiguration	This register is used to
base +0x030					configure the PrimeCell DMA
					controller.

DMA controller	Read/write	16	0x0000	DMACSync	This register enables or
base + 0x34					disables synchronization logic
					for the DMA request signals.

ARM DDI 0196C

3-7

Programmer’s Model

Table 3-1 PrimeCell DMA controller register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

DMA controller	Read/write	32	0x00000000	DMACC0SrcAddr	DMA channel 0 source
base +0x100					address.

DMA controller	Read/write	32	0x00000000	DMACC0DestAddr	DMA channel 0 destination
base + 0x104					address.

DMA controller	Read/write	32	0x00000000	DMACC0LLI	DMA channel 0 linked list
base + 0x108					address.

DMA controller	Read/write	32	0x00000000	DMACC0Control	DMA channel 0 control.
base + 0x10C

DMA controller	Read/write	19	0x00000	DMACC0Configuration	DMA channel 0 configuration
base + 0x110					register.

DMA controller	Read/write	32	0x00000000	DMACC1SrcAddr	DMA channel 1 source
base + 0x120					address.

DMA controller	Read/write	32	0x00000000	DMACC1DestAddr	DMA channel 1 destination
base + 0x124					address.

DMA controller	Read/write	32	0x00000000	DMACC1LLI	DMA channel 1 linked list
base + 0x128					address.

DMA controller	Read/write	32	0x00000000	DMACC1Control	DMA channel 1 control.
base + 0x12C

DMA controller	Read/write	19	0x00000	DMACC1Configuration	DMA channel 1 configuration
base + 0x130					register.

DMA controller	Read/write	32	0x00000000	DMACC2SrcAddr	DMA channel 2 source
base + 0x140					address.

DMA controller	Read/write	32	0x00000000	DMACC2DestAddr	DMA channel 2 destination
base + 0x144					address.

DMA controller	Read/write	32	0x00000000	DMACC2LLI	DMA channel 2 linked list
base + 0x148					address.

DMA controller	Read/write	32	0x00000000	DMACC2Control	DMA channel 2 control.
base + 0x14C

DMA controller	Read/write	19	0x00000	DMACC2Configuration	DMA channel 2 configuration
base + 0x150					register.

3-8

ARM DDI 0196C

					Programmer’s Model
			Table 3-1 PrimeCell DMA controller register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

DMA controller	Read/write	32	0x00000000	DMACC3SrcAddr	DMA channel 3 source
base + 0x160					address.

DMA controller	Read/write	32	0x00000000	DMACC3DestAddr	DMA channel 3 destination
base + 0x164					address.

DMA controller	Read/write	32	0x00000000	DMACC3LLI	DMA channel 3 linked list
base + 0x168					address.

DMA controller	Read/write	32	0x00000000	DMACC3Control	DMA channel 3 control.
base + 0x16C

DMA controller	Read/write	19	0x00000	DMACC3Configuration	DMA channel 3 configuration
base + 0x170					register.

DMA controller	Read/write	32	0x00000000	DMACC4SrcAddr	DMA channel 4 source
base + 0x180					address.

DMA controller	Read/write	32	0x00000000	DMACC4DestAddr	DMA channel 4 destination
base + 0x184					address.

DMA controller	Read/write	32	0x00000000	DMACC4LLI	DMA channel 4 linked list
base + 0x188					address.

DMA controller	Read/write	32	0x00000000	DMACC4Control	DMA channel 4 control.
base + 0x18C

DMA controller	Read/write	19	0x00000	DMACC4Configuration	DMA channel 4 configuration
base + 0x190					register.

DMA controller	Read/write	32	0x00000000	DMACC5SrcAddr	DMA channel 5 source
base + 0x1A0					address.

DMA controller	Read/write	32	0x00000000	DMACC5DestAddr	DMA channel 5 destination
base + 0x1A4					address.

DMA controller	Read/write	32	0x00000000	DMACC5LLI	DMA channel 5 linked list
base + 0x1A8					address.

DMA controller	Read/write	32	0x00000000	DMACC5Control	DMA channel 5 control.
base + 0x1AC

DMA controller	Read/write	19	0x00000	DMACC5Configuration	DMA channel 5 configuration
base + 0x1B0					register.

ARM DDI 0196C

3-9

Programmer’s Model

Table 3-1 PrimeCell DMA controller register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

DMA controller	Read/write	32	0x00000000	DMACC6SrcAddr	DMA channel 6 source
base + 0x1C0					address.

DMA controller	Read/write	32	0x00000000	DMACC6DestAddr	DMA channel 6 destination
base + 0x1C4					address.

DMA controller	Read/write	32	0x00000000	DMACC6LLI	DMA channel 6 linked list
base + 0x1C8					address.

DMA controller	Read/write	32	0x00000000	DMACC6Control	DMA channel 6 control.
base + 0x1CC

DMA controller	Read/write	19	0x00000	DMACC6Configuration	DMA channel 6 configuration
base + 0x1D0					register.

DMA controller	Read/write	32	0x00000000	DMACC7SrcAddr	DMA channel 7 source
base + 0x1E0					address.

DMA controller	Read/write	32	0x00000000	DMACC7DestAddr	DMA channel 7 destination
base + 0x1E4					address.

DMA controller	Read/write	32	0x00000000	DMACC7LLI	DMA channel 7 linked list
base + 0x1E8					address.

DMA controller	Read/write	32	0x00000000	DMACC7Control	DMA channel 7 control.
base + 0x1EC

DMA controller	Read/write	19	0x00000	DMACC7Configuration	DMA channel 7 configuration
base + 0x1F0					register.

DMA controller	Read	8	0x80	DMACPeriphID0	Peripheral identification
base +0xFE0					register bits 7:0.

DMA controller	Read	8	0x10	DMACPeriphID1	Peripheral identification
base +0xFE4					register bits 15:8.

DMA controller	Read	8	0x04	DMACPeriphID2	Peripheral identification
base +0xFE8					register bits 23:16.

DMA controller	Read	8	0x0A	DMACPeriphID3	Peripheral identification
base +0xFEC					register bits 31:24.

DMA controller	Read	8	0x0D	DMACPCellID0	PrimeCell identification
base +0xFF0					register bits 7:0.

3-10

ARM DDI 0196C

					Programmer’s Model
			Table 3-1 PrimeCell DMA controller register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

DMA controller	Read	8	0xF0	DMACPCellID1	PrimeCell identification
base +0xFF4					register bits 15:8.

DMA controller	Read	8	0x05	DMACPCellID2	PrimeCell identification
base +0xFF8					register bits 23:16.

DMA controller	Read	8	0xB1	DMACPCellID3	PrimeCell identification
base + 0xFFC					register bits 31:24.

ARM DDI 0196C

3-11

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