Programmer’s Model

3.4Interrupts

Refer to Interrupt generation logic below for a functional description of the interrupt generation logic.

Two individual maskable active HIGH interrupts, ACIRXINTR and ACITXINTR, are generated by the PrimeCell ACI. Each of these interrupts may be enabled or disabled by changing the mask bits TIE and RIE in ACICR. Setting the appropriate mask bit HIGH enables the corresponding interrupt. This allows for a system interrupt controller to provide the mask registers for each interrupt. In this way a global interrupt service routine would be able to read the entire set of sources from one wide register in the system interrupt controller. This is an attractive option where the time to read from the peripheral registers is significant compared to the CPU clock speed in a real time system.

The interrupts are also output as a combined single interrupt that is an OR function of the individual masked sources. ACIINTR is asserted if any of the two individual interrupts above are asserted and unmasked. This output can be connected to the system interrupt controller to provide another level of masking on a per-peripheral basis. This allows use of modular device drivers that always know where to find the interrupt source control register bits.

The status of the individual interrupt sources can be read from ACISR.

3.4.1Interrupt generation logic

The two maskable active HIGH interrupts, ACIRXINTR and ACITXINTR, and the combined single interrupt ACIINTR that are generated by the ACI, are described below:

ACIRXINTR The receive interrupt is asserted when the ACI receive FIFO is greater than or equal to half full (the FIFO contains eight or more words and the mask bit RIE is set in ACICR).

The receive interrupt is cleared when the FIFO becomes less than half full (the FIFO contains less than eight words).

ACITXINTR The transmit interrupt is asserted when the ACI transmit FIFO is at least half empty (the FIFO contains less than eight words and the mask bit TIE is set in ACICR).

The transmit interrupt is cleared by filling the transmit FIFO to more than half full (the FIFO contains more than eight words).

Programmer’s Model

The individual masked interrupt outputs are also combined into a single output that is an OR function of the individual sources. This output can be connected to the system interrupt controller to provide another level of masking on an individual per-peripheral basis.

The transmit interrupt ACITXINTR is not qualified with the ACI Transmit Enable signal, which allows operation in one of two ways. Data can be written to the transmit FIFO prior to enabling the ACI, and then interrupts can be enabled. Alternatively, the ACI can be transmit enabled and interrupt enabled so that data values are written to the transmit FIFO by the Interrupt Service Routine.

Programmer’s Model