Functional Overview

2.5DMA interface bus protocol

The interface to the DMA Controller (DMAC) includes the signals listed in Table A-2 on page A-3.

The DMA signals are only connected to the receive and transmit FIFOs of channel 1 and you must ensure that the data requiring DMA is stored in these FIFOs. System requirements determine if the DMA channels are to be used.

In the receive FIFO, the DMAC monitors all of the REQ signals. When AACIDMABREQRX is asserted a burst of data is available and, during this time, AACIDMASREQRX is ignored. When the amount of data remaining is less than a burst, AACIDMASREQRX is asserted, allowing the DMAC to perform single transfers, as data becomes available. AACIDMABREQRX and AACIDMASREQRX need not be mutually exclusive. Essentially they are tidemarks from the FIFO, modified only to ensure that they clear for at least one cycle after a transfer has completed (as indicated by AACIDMACLRRX).

The PrimeCell AACI indicates to the DMAC through the AACIDMALBREQRX and AACIDMALSREQRX that the receive FIFO contains the last amount of data to be transferred before the DMAC can reassign the channel. If there has been RxTimeout in the AACISR generated, and there are only four words in the FIFO to be read by the DMAC, the AACIDMALBREQRX signal is asserted. If there is only one word of data in the FIFO and a RxTimeout in AACISR generated then the AACIDMALSREQRX is asserted. One of these two signals must be asserted in order for the DMAC to initiate the appropriate transfer then move onto the next link list item. If the FIFO is empty, and an internal Timeout (the internal Timeout uses the same TOC as RxTimeout) is generated, it is necessary for the PrimeCell AACI to tell the DMAC the last data has been sent. This is achieved through the AACIRXTOFEINTR interrupt service routine that writes to the DMAC. The AACIDMALSREQRX and AACIDMALBREQRX signals are mutually exclusive to AACIDMASREQRX and AACIDMABREQRX signals.

As the transmission data is under software control, the DMAC can be programmed with the descriptor (start location in memory, destination location, address, size of data) required for the data to be sent. When all the data is sent to the transmit FIFO and no more descriptors are set up for this channel during the transmission the DMAC can then go to the next link list item or generate a DMA interrupt.

The DMAC only transfers data to the transmit FIFO of the peripheral when the peripheral is capable of accepting a full burst of data. If the total amount of data remaining in the DMAC is less than a burst (for example, three words to be transferred in total), then the DMAC uses a series of single transfers to transfer the remaining data. The PrimeCell AACI does not need to produce AACIDMASREQTX.

Functional Overview

In compact mode the DMA request signals are only generated when there is an even amount of data in the FIFO channel. This means that the AACIDMASREQRX in compact mode is generated when there are two words in the FIFO. You must ensure that only valid double words are read in compact mode, that is, under interrupt or DMA control. This is because it is possible that while a read of the FIFO is taking place new data can be received that is valid until the second data word is received.

The DMA interface signals are synchronous with the PCLK clock.

Functional Overview