Digital Design VHDL Laboratory

1.VHDL - Hardware Design Software Approach

pepe, 5/23/96

1. VHDL - Hardware Design Software Approach

1.1 Introduction

Software programming, no doubt, is a common skill required by all college engineering students. Such knowledge is indispensable for utilizing a computer as a tool for achieving greater engineering goals in both the classroom and the real world. Programming tasks for applications range vary in level of detail and complexity. The readability of programming language constructs span from a very low level, which is almost at the hardware level such as PAL programming, to a high level such as application level programming. Good examples of application programming are database, UNIX shell scripts, DOS batch file, and SPICE circuit simulation. Almost all programming language lie between these two ends. The major difference between programming languages is their programming complexity which affects such things as development time. Sequential programming is most common among programming languages. Examples of sequential languages are BASIC, FORTRAN, Pascal and C. Besides sequential programming, there are other programming paradigms: parallel programming and object based programming. These paradigms are new for most people, and they will be introduced during the process of learning VHDL. VHDL is not much different from conventional programming languages, except it uses sequential, parallel, and object based software paradigms to achieve its goal: namely, digital hardware simulation and synthesis. In other words, a VHDL program is used to specify, to model, and to “create” digital hardware.

VHDL stands for VHSIC (Very High Speed Integrated Circuit) Descriptive Language. VHDL is promoted by the Department of Defense (DOD) mainly to facilitate the standardization of all digital hardware design. VHDL serves as a documentation tool at the beginning to describe a system in a unified manner across the cooperative group of a project. VHDL was started in early 1980 inside of DOD and eventually got standardized by IEEE with the name standard 1076 (IEEE-STD-1076) in 1987. Although further enhancements have been added to the later version of VHDL, for example standard 1164 (IEEE- STD-1164), standard 1076 will be sufficient to learn and explore most of the language feature.

1.1.1 Sequential Programming

This type of programming is characterized by the sequential nature of program flow. Popular programming languages such as Pascal, C, BASIC and FORTRAN are the examples in this category. It is also called imperative programming because programming statements to be executed are imperative. Programs are executed in sequential order and a statement is executed following the statement that precedes it in the proogramm. There is always a clear decision as far as which the next program statement is to be executed next. In summary, in sequential programming, there is no ambiguity as far as the statements execution order is concerned.

In VHDL syntax, the statements after the reserved keyword process or within the process block will be executed in sequential order. Typical VHDL sequential statements are condition statements, loop statements, and assignment statements. The syntax of each type of statement can be found in any reasonably thorough VHDL tutorial text book.

1.1.2 Parallel Programming

The parallel programming concept is a more difficult programming paradigm to grasp for people used to sequential programming. The parallel programming concept is straightforward and is expressed through

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Copyright 1996, CERL / EE, V1.00

Digital Design VHDL Laboratory

1.VHDL - Hardware Design Software Approach

pepe, 5/23/96

its name; statements are executed in parallel. Moreover, the process of executing statements in parallel mimics the real world phenomena and thus coincide better with the behavior of digital circuits. In parallel processing, the application of parallel programmingg, programs executed in parallel have the advantage of boosting program execution speed versus the equivalent sequential program. In the area of VHDL programming, the goal is to mimic the physical digital system. Due to the fact that hardware operates executed in parallel, to capture the functionality of the hardware, it is important for VHDL to have the features to facilitate the modeling of such behavior.

Parallel program statements, as the name suggests, are the statements that can be executed in parallel. Parallel statements are less intuitive to use due to their nondeterministic nature. Ideally, all parallel statements should be executed at the same time. However, in the popular Von Neumann machine or sequential computer world (eg., PCs and worstations), only sequential statements can be directly executed. Therefore, parallel programming must be simulated on a sequential machine. When simulating parallel statements, due to the fact that statements are executed in parallel and random order, it is crucial that the execution order be irrelevant and not affect the result.

An example of a parallel system is shown in Figure 1-1. It describes a digital hardware circuit where four inputs and one output are involved. Inputs A, B, C and D are fed into two AND gates, and the outputs of these AND gates, E and F, are then fed into an OR gate whose output is shown below(see Figure 1-1).

A E

B

G

C

D F

Figure 1-1. AND-OR Gates

A piece of simple VHDL code shown in Listing 1-1 describes the circuit above. Notice the section after dataflow_machine architecture in the code. Three statements, a, b, and c describe AND and OR logical assignments. These statements can be rearranged in any order, and the simulated output G should still be the same.

-- Sum of product example entity sop is

port ( a, b, c, d: in bit; e, f: inout bit;

g: out bit); end sop;

architecture dataflow_machine of sop is begin

-- Begin parallel statements

end dataflow_machine;

Listing 1-1. Simple VHDL Code for Dataflow Modeling

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Copyright 1996, CERL / EE, V1.00

Digital Design VHDL Laboratory

1.VHDL - Hardware Design Software Approach

pepe, 5/23/96

The result G will be the same if the statements assigning E, F and G outputs were placed in any order. Any data arriving at the inputs A, B, C, and D will pass through the AND and OR gates in continuous time fashion. Whatever shown up at A, B, C or D inputs will be reflected at the intermediate outputs E and F and at the final output G. Thus, output G should change instantly according to the essence of parallel programming. In the world of hardware execution, there is always a delay when data pass through gates. The VHDL code of hardware synthesis is mapped into a Cypress CPLD 375 device and fitted with optimization disabled. The simulation of the mapped Cypress 375 PCLD shows that there is a delay of about 5 ticks between each logical gate. Notice that ticks from VHDL simulation below do not represent any real-time. Instead, a simulation tick is simply a unit of delay of simulation time. In the real world, gates delay are on the order of nanoseconds (10-9 sec).

Figure 1-2. AND-OR Gate Propagation Output

Intuitively, the parallel VHDL statements above should be executed in the order: c, a and b. However, the hardware VHDL simulator handles the situation differently. The VHDL simulator executes the parallel statements in clock random order fashion.

Notice that VHDL statements written within the process block have been executed sequentially. Therefore, all VHDL statements outside of the process block will be executed in parallel. For example, two process blocks can be executed in parallel. To resolve sequential statements inside of each process block, VHDL uses the concept of delta time slots for each clock tick. In each clock tick, the simulator allocates however many sub-ticks called delta for simulating the instantaneous statement execution. Individual parallel statement are being executed at delta ticks. A simulated clock tick will only move forward when the delta tick yields consistent outputs. An example above would be stable E, F, and G outputs.

1.1.3 Object Based Programming

Objected based programming is different from the sequential and parallel paradigms. It should be treated more like a methodology than a paradigm. Objected based methodology basically enforces structure into VHDL. This facilitates the systematic construction of large and complicate digital system. Object based programming also supports the concept of abstract data types enabling the VHDL engineer to construct custom data types and operations and then to store them systematically for future VHDL projects. This is the concept of VHDL code reuse. Since the feature of breaking VHDL code into small components and libraries is already built into the language, it provides the VHDL designer with the structural divide and conquer technique when building larger systems. Moreover, the concept of code reuse definitely saves

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Copyright 1996, CERL / EE, V1.00

Digital Design VHDL Laboratory

1.VHDL - Hardware Design Software Approach

pepe, 5/23/96

system development time. In summary, object based features are extremely useful for VHDL code development, management, and reusability.

1.1.4 Programmable Circuits

Digital design technology has evolved greatly in recent years. This can be seen in the field of ever changing microprocessor design where complexity and performance double every year. With improvements to digital hardware technology, the criteria used to determine a design’s goodness remain

the same, and they are listed in Listing 1-2.

These five criteria are borrowed from the book, Object-oriented Software Construction, by Bertrand Meyer. Although, they were used to describe software quality, the concepts are also appropriate to be used on hardware. Notice that hardware design technical merits such as speed and cost are not mentioned because they highly depend on the state of technology and market demand.

The word, flexibility, sums up all these criteria above. The practice of digital design nowadays must be flexible. Thus, the trend is to replace ridged discrete logic component with programmable devices to maximize hardware flexibility.

Traditional programmable circuits comes in three flavors of simple combinational logic circuit: Programmable Read Only Memory(PROM), Programmable Logic Array(PLA), and Programmable Array Logic(PAL). All these three devices contain similar hardware structure of AND and OR arrays. Input goes from the AND array to the OR array. The difference is that PROM contains fixed AND and programmable OR arrays, PAL contains programmable AND and fixed OR arrays, and PLA contains programmable AND and OR arrays. (See the figure Figure 1-3.)

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Copyright 1996, CERL / EE, V1.00