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EMI and layout fundamentals for switched mode circuits

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Parasitic inductances of input loop explicitly shown:

Q1

+

i1(t)

D1

Addition of bypass capacitor confines the pulsating current to a smaller loop:

Q1

+

ig(t)

i1(t)

D1

high frequency currents are shunted through capacitor instead of input source

ECEN 5797 Power Electronics 1

10

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

 

 

 

Even better: minimize area of the high frequency loop, thereby minimizing its inductance

Q1

+

D1

 

B fields nearly cancel

i1

loop area A c

i1

ECEN 5797 Power Electronics 1

11

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

 

 

 

Forward converter

Two critical loops:

 

 

 

 

+

i

(t)

i2(t)

 

1

 

 

Solution:

 

 

 

 

+

 

 

 

 

 

 

 

 

ECEN 5797 Power Electronics 1

 

 

12

Department of Electrical and Computer Engineering

 

 

University of Colorado at Boulder

 

 

 

 

Unwanted coupling of signals

via impedance of ground connections

++

Power supplies

+48 volts

+15 volts

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Stage 1

 

 

 

Stage 2

 

 

Stage 3

 

input

output

input

output

input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All currents must flow in closed paths: determine the entire loop in which large currents flow, including the return connections

Ground (zero potential) references may not be the same for every portion of the system

ECEN 5797 Power Electronics 1

13

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

 

 

 

Example: suppose the ground connections are

+48 volts

i3

 

 

 

+15 volts

i2

 

 

i1(t)

 

 

 

 

 

 

 

 

 

 

 

 

+

+

 

 

 

Stage 1

 

 

 

 

 

 

 

 

 

 

 

+

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

v

 

 

 

 

 

 

 

 

v

out

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

in

 

 

 

 

 

 

 

 

 

 

 

 

 

Zg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

i2 + i 3

 

 

 

 

 

 

 

 

 

 

 

 

Stage 2

 

 

Stage 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

vin2 = vout1 Zg (i2 + i 3)

“Noise” from stages 2 and 3 couples into the input to stage 2

This represents conducted EMI, or specifically corruption of the ground reference by system currents

ECEN 5797 Power Electronics 1

14

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

 

 

 

 

Example: gate driver

 

 

line input

 

 

 

 

+15 volt supply

 

 

converter

 

 

 

power

 

 

 

 

stage

+

+

 

ig(t)

 

 

 

 

 

 

 

 

analog

PWM

gate

power

 

control

 

control

 

chip

driver

MOSFET

 

chip

 

 

 

 

 

ig(t)

 

 

 

ECEN 5797 Power Electronics 1

15

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

 

Solution: bypass capacitor and close coupling of gate and return leads

line input

converter +15 volt supply power

stage

+

+

analog

PWM

gate

power

control

control

driver

MOSFET

chip

chip

 

 

High frequency components of gate drive current are confined to a small loop

A dc component of current is still drawn output of 15V supply, and flows past the control chips. Hence, return conductor size must be sufficiently large

ECEN 5797 Power Electronics 1

16

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

 

 

 

About ground planes

Current i(t) flowing in wire

return current i(t) flows in ground plane directly under wire

wire

ground plane

Inductance of return connections is minimized

Hence ground planes tend to exhibit lower impedance ground connections, and more nearly equipotential ground references

Ground planes are especially effective in the analog control portions of switching regulator circuits

But it is still possible to observe significant coupling of noise in ground, by

poor layout of ground plane, or

high resistance of ground plane

ECEN 5797 Power Electronics 1

17

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

 

 

 

A poor ground plane layout

power supply

power supply return

power supply

power supply return

ground plane

 

 

 

 

 

 

 

 

Return current of noisy

 

 

 

 

 

 

 

 

circuit runs

 

 

 

 

 

 

 

 

underneath sensitive

 

 

 

 

 

 

 

 

circuits, and can still

 

 

 

 

 

 

 

 

sensitive

 

sensitive

 

Noisy

 

 

corrupt their ground

circuit

 

circuit

 

circuit

 

 

 

 

 

 

 

 

 

 

references

ground plane

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

sensitive

 

sensitive

v

Noisy

 

circuit

 

circuit

circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

A solution is to remove the noisy circuit from the ground plane. One could then run a separate ground wire for the noisy circuit. The only drawback is that noise can be coupled into the input signal v.

ECEN 5797 Power Electronics 1

18

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

 

 

 

Coupling of signals via magnetic fields

 

 

i(t)

 

Loop containing ac

 

 

 

current i(t)

 

 

 

generates B field

 

mutual flux

 

 

 

 

which links another

 

+

 

 

 

di (t)

conductor,

 

v ( t ) = L M

inducing an

 

dt

 

 

unwanted voltage

 

 

v(t)

 

 

 

 

 

ECEN 5797 Power Electronics 1

19

Department of Electrical and Computer Engineering

University of Colorado at Boulder

 

 

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