12.General-purpose microprocessors

Figure 5. Connections between the datapath and the control unit for our general microprocessor.

Combining the datapath and control unit entities together is easily accomplished by writing a higher level VHDL entity using the structural model as shown in Listing 3.

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

USE IEEE.std_logic_arith.all;

ENTITY cpu IS PORT ( clk_cpu: std_logic; rst_cpu: IN std_logic;

input_cpu: IN std_logic_vector(7 DOWNTO 0); output_cpu: OUT std_logic_vector(7 DOWNTO 0));

END cpu;

ARCHITECTURE structure OF cpu IS

COMPONENT ctrl PORT ( clk_ctrl: IN std_logic; rst_ctrl: IN std_logic;

muxsel_ctrl: OUT std_logic_vector(1 DOWNTO 0); imm_ctrl: OUT std_logic_vector(7 DOWNTO 0); accwr_ctrl: OUT std_logic;

rfaddr_ctrl: OUT std_logic_vector(2 DOWNTO 0); rfwr_ctrl: OUT std_logic;

alusel_ctrl: OUT std_logic_vector(2 DOWNTO 0); shiftsel_ctrl: OUT std_logic_vector(1 DOWNTO 0); outen_ctrl: OUT std_logic;

zero_ctrl: IN std_logic; positive_ctrl: IN std_logic);

END COMPONENT;

COMPONENT dp PORT ( clk_dp: IN std_logic;

SIGNAL C_immediate: std_logic_vector(7 DOWNTO 0); --SIGNAL D_immediate: std_logic_vector(7 DOWNTO 0);

SIGNAL C_accwr,C_rfwr,C_outen,C_zero,C_positive: std_logic; SIGNAL C_muxsel,C_shiftsel: std_logic_vector(1 DOWNTO 0); SIGNAL C_rfaddr,C_alusel: std_logic_vector(2 DOWNTO 0);

BEGIN

U0: ctrl PORT

MAP(clk_cpu,rst_cpu,C_muxsel,C_immediate ,C_accwr,C_rfaddr,C_rfwr,C_alusel,C_shif tsel,C_outen,C_zero,C_positive);

U1: dp PORT

MAP(clk_cpu,rst_cpu,C_muxsel,C_immediate ,input_cpu,C_accwr,C_rfaddr,C_rfwr,C_alu sel,C_shiftsel,C_outen,C_zero,C_positive ,output_cpu);

--D_immediate <= C_immediate; END structure;

Listing 3. CPU – connecting the control unit with the datapath.

12.6 Top-level Computer

In order to actually test out our custom general microprocessor, we need to connect it to the three basic components as defined in the Von Neuman architecture of a computer system, namely, an input, an output and a memory.

12.6.1 Input

Our computer input consists of eight simple dip switches for binary input of a number.

12.6.2 Output

Our computer output consists of two 7-segment LEDs. The 8-bit output from the CPU datapath is decoded so that the eight bit binary value is displayed as two decimal digits on the two 7-segment LEDs.

12.6.3 Memory

12.6.4 Clock

For our system clock, we use the built-in 25MHz clock that is available on the development board. In order to see some intermediate actions by the CPU, we have used a clock divider to slow down the clock.

12.6.5 VHDL Code for the Complete Computer

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

USE IEEE.std_logic_arith.all;

ENTITY computer IS PORT (

clock_25MHz: IN std_logic; -- from pin 91 of UP2 reset: IN std_logic;

input_comp: IN std_logic_vector(7 DOWNTO 0); digit1_comp: OUT std_logic_vector(1 TO 8); digit2_comp: OUT std_logic_vector(1 TO 8));

END computer;

ARCHITECTURE structure OF computer IS

COMPONENT clk_generator PORT (

END COMPONENT;

COMPONENT cpu PORT ( clk_cpu: IN std_logic; rst_cpu: IN std_logic;

input_cpu: IN std_logic_vector(7 DOWNTO 0); output_cpu: OUT std_logic_vector(7 DOWNTO 0));

END COMPONENT;

COMPONENT output PORT (

number: IN std_logic_vector(7 DOWNTO 0); digit1, digit2: OUT std_logic_vector(1 TO 7));

END COMPONENT;

SIGNAL clk: STD_LOGIC;

SIGNAL resetN: STD_LOGIC;

SIGNAL C_outcpu: std_logic_vector(7 DOWNTO 0);

SIGNAL C_digit1,C_digit2: std_logic_vector(1 TO 7);

BEGIN

U0: clk_generator PORT MAP(clock_25MHz, open, open, clk, open, open, open, open);

U1: cpu PORT MAP(clk,resetN,input_comp,C_outcpu); U2: output PORT MAP(C_outcpu,C_digit1,C_digit2);

digit1_comp <= C_digit1 & '1' WHEN C_outcpu < "01100100" ELSE C_digit1 & '0';

digit2_comp <= C_digit2 & '1'; resetN <= NOT reset;

END structure;

Listing 4. Top-level computer.

12.7 Examples

Example 12.1

In this example, we will implement the multiplication program on our CPU. Figure 6(a) shows the disassembled code for the multiplication program.

(b)

(c)

(d)

Figure 6. Multiplication of 13 × 11: (a) multiplication program; (b) initialization of RF(0)=0, RF(1)=13 and RF(2)=11; (c) one iteration of the loop; (d) last iteration with the result 143 in RF(0).