диафрагмированные волноводные фильтры / 517b7f9e-ca2f-4c52-8597-a30fcfa2a484

ABSTRACT— Substrate integrated waveguide (SIW) uses rows of plated through holes to emulate the intact vertical walls of a waveguide circuit. It succeeds in the design of H-plane circuits but not the E-plane circuits because an E-plane circuit requires longitudinal current on the vertical walls that is not supported by SIW. In this paper, a novel substrate integrated E-plane waveguide (SIEW) is presented. In SIEW, additional copper strips are inserted at the middle layer of the structure while the copper plated through holes remain unchanged. Consequently, the vertical current flows on the through holes and the longitudinal current flows along the middle strips to meet the wave propagation requirement in the E-plane waveguide circuit. The insertion loss, cutoff frequency, and propagation constant of the SIEW are investigated. As examples, an empty SIEW, a bandpass septum SIEW filter, and a dual polarized SIEW horn antenna are designed using the SIEW technique. All of them are constructed and their performance is measured to validate the design.

INDEX TERMS— dual-polarized antennas, waveguide filters, waveguide antennas, planar waveguides

I. INTRODUCTION

Substrate integrated waveguide (SIW) is a transmission line type that has recently been extensively studied [1], [2], [3], [4]. It is a technique to implement planar waveguide circuits and antennas on a piece of printed circuit board (PCB). SIW provides compact, lightweight and highly integrated designs for microwave and millimeter wave applications. In SIW, rows of copper plated through holes are drilled in the PCB to emulate the vertical walls of a planar waveguide circuit. The top and bottom copper plating of the PCB are used as the horizontal walls. Since its invention, many SIW devices were designed, such as filters [5], [2], [6], a six-port junction [7], a diplexer [8], a coupler [9], hybrid rings [10], [6], horn antennas [11], [12], slot antennas [13], [14] etc.

However, all the SIW designs that rely on the plated through holes fall into the H-plane types such that the electric field is perpendicular to the planar structure. In fact, the conventional SIW cannot be used to realize the E-plane type of waveguide circuits where the electric field is parallel to the planar circuit because the signal will leak from the gaps between plated through holes. E-plane waveguide devices have been widely used in the microwave and millimeter wave industry for a long time [15], [16], [17]. Compared to its H-plane counterpart, an E-plane waveguide device has a smaller footprint on the two-dimensional plane because its width can be less than a half wave length. Therefore, many compact designs were

The authors are with the Department of Electrical and Computer Engineering and Technology, Minnesota State University, Mankato, MN 56001, USA

achieved using the E-plane waveguide, such as a filter [18], a four way power divider [19], a multiplexer [20], a directional coupler [21], etc. Considering the advantages of the E-plane waveguide, its implementation on PCB is desirable.

The concept of substrate integrated E-plane waveguide (SIEW) was introduced recently to address the aforementioned problem [22]. Similar to the E-plane waveguide, the SIEW allows a more compact waveguide circuit design on PCB. The SIEW has additional copper strips at the middle layer of the PCB to direct the longitudinal current. These strips are key to guiding horizontally polarized fields. However, in [22], only preliminary simulated results were reported. The presented SIEW circuits were excited by waveguide ports in the simulated model without the discussion of a practical feeding mechanism. The prototyping of such circuits were not discussed either. Recently, an E-plane sectoral horn antenna and an antenna array based on the SIEW were reported [23]. Such an E-plane horn antenna can be naturally integrated with other SIEW circuits.

This paper is the first to provide a complete investigation of the SIEW, from the theoretical study to the practical circuit design, including both the numerical analysis and experimental validation. First, the analytical field solutions in a planar waveguide circuit are used to explain the success of the SIW in the design of H-plane circuits and its failure in the E- plane circuits. This anlytical explanation leads to structure of SIEW for the design of E-plane circuits. Next, it is the first time in this paper the wave guidance characteristics of the SIEW such as the insertion loss, cutoff frequency, propagation constant and peak power handling capacity are explored. Three practical circuits are presented with simulated and measured results to validate the SIEW concept and designs. Moreover, this paper also presents a newly discovered advantage of the SIEW: its capability to design dual polarized integrated waveguide circuits. This new feature is verified by the design of a novel orthomode transducer (OMT) and dual polarized substrate integrated horn antenna.

II. SIW’S SUCCESS IN H-PLANE AND FAILURE IN E-PLANE

WAVEGUIDE CIRCUITS

An H-plane waveguide circuit is placed on the x-y plane as shown in Fig. 1(a). It is excited by an H-plane waveguide port under TE10 mode so that the excited electric field is in the z direction only and is independent of the z coordinate. Because of the constant height of the structure, Ex = Ey = 0 in the entire circuit, which leads to Hz = 0 based on the Maxwell

Fig. 1. (a) An H-plane waveguide circuit and (b) its SIW implementation

Fig. 2. (a) An E-plane waveguide and (b) its SIW implementation that gives

(c) the corresponding total electric field distribution

equation

Consequently, on any vertical wall, the longitudinal current

density l z due to the boundary condition ~ ~ J = H = 0 J = nˆ×H

assuming the longitudinal direction is tangential to the vertical wall and orthogonal to the z direction. Therefore, the electric current on vertical walls flows only in the z direction, which can be supported by the copper plated through hole in its SIW implementation as shown in Fig. 1(b).

If the same SIW structure is applied to implement E-plane waveguide circuit on PCB, the results are unsatisfactory. Fig. 2(a) shows an E-plane waveguide where the wide walls are vertical and the narrow walls are horizontal. Its counterpart SIW implementation is shown in Fig. 2(b) where the narrow walls are intact as part of the copper plating and the wide walls are synthesized using two rows of copper plated through holes. If the fundamental TE10 mode is excited, the electric field is parallel to the PCB. The simulated field distribution is illustrated in Fig. 2(c) which demonstrates the failure of the SIW to guide signals in this case. Such failure can be explained by examining the electric current density on the vertical walls.

Fig. 3(a) shows a typical E-plane waveguide circuit that is placed on the x-y plane. It is excited by an E-plane rectangular waveguide under the TE10 mode. The electric field is parallel to the circuit and has a sinusoidal distribution in the z direction

Fig. 3. (a) A planar E-plane waveguide circuit, (b) its SIW implementation and (c) its SIEW implementation

as

~ (x, y, z) = [ˆxE (x, y) + yEˆ (x, y)] (k z)

E x y SIN z (2)

where kz = π/h with h as the thickness of the circuit. Plug

(2) into (1) gives the magnetic field as

With the fact that the electric current density on the vertical walls equals the tangential magnetic field, but rotates 90◦, there exist both vertical current density Jz and longitudinal current density Jl as

where ˆ is the unit vector in the longitudinal direction of the l

vertical wall. The vertical current Jz in (4) can be supported by the copper plated through holes in Fig. 3(b), but there is no structure that allows the flow of longitudinal current Jl in

(5). In fact, the gaps between the copper plated through holes act as slot antennas because they cut the electric current path. Consequently, electromagnetic energy leaks from those slot antennas as observed in Fig. 2(c).

III. SIEW STRUCTURE

Since the SIW cannot be used to implement the E-plane waveguide circuit on PCB, a new transmission line type needs to be invented. As discussed before, the failure of the SIW to implement E-plane waveguide circuits is due to the lack of structure that allows the flow of longitudinal current. In other words, if a new structure is introduced into the existing SIW to support the longitudinal electrical current, the problem could be solved. With the help of multilayer PCB technology, copper strips can be inserted into the waveguide circuit as additional paths for electric current. The optimum height of the inserted copper strips is determined based on the electrical

z direction and so has its peak value at the middle layer of the planar circuit. Therefore, the copper strips should be inserted at the middle layer of the waveguide circuit and follow the longitudinal direction of the vertical walls to support the flow of longitudinal electric current. This new transmission line type is referred to as substrate integrated E-plane waveguide (SIEW) and is illustrated in Fig. 3(c).

As an example, an E-plane waveguide is implemented using the SIEW as shown in Fig. 4. The substrate has a total height of 5.08 mm, ǫr = 13.3, and tanδ = 0.002. Simulation analysis using Ansys HFSS [24] reveals that the SIEW is very promising to implement E-plane waveguide circuits on PCB. In the simulated model, two 0.2 mm long pieces of ridged waveguide are used as the ports in order to obtain S

Fig. 4. (a) SIEW structure and (b) its middle layer layout

Fig. 5. Total electric field distribution of the SIEW in (a) the transverse cross section and in (b) the longitudinal cross section with W = 3.7 mm, D = 1 mm, G = 0.5 mm and S = 0.1 mm

parameters. The ridge is simply the extension of the SIEW’s middle strip. The propagation constant of the SIEW can be obtained using the phase of S21 after the phase delay of the ridged waveguide sections are subtracted. Fig. 5(a) shows the electric field distribution in the transverse cross section. It is very close to that of a conventional E-plane waveguide with electric field in the horizontal direction. Fig. 5(b) illustrates the field distribution in the longitudinal cross section. It clearly demonstrates the SIEW is able to guide the electromagnetic wave whose electric field is parallel to the PCB.

As illustrated in Fig. 4(b), the SIEW has four design parameters: the hole diameter D, the through hole gap g, the waveguide width W , and the middle strip insertion s. Compared to the SIW, the middle strip insertion s is a unique parameter of the SIEW. Its value significantly affects the wave transmission performance because it determines how effective the flow of the longitudinal current is supported. For example, with all the other parameters fixed as W = 3.7 mm, D = 1 mm, and g = 0.5 mm, the insertion loss per substrate wavelength of the SIEW is plotted in Fig. 6 for different s values. As shown, a positive insertion value s is recommended to achieve low insertion loss. When the s value reaches the negative region, the guidance of the longitudinal current is less effective and causes energy leakage from the gaps between the plated through holes. This occurs because the middle strip acts as the interior surface of the waveguide’s vertical wall to guide longitudinal current and needs to be inserted into the waveguide with a positive s value.

The cutoff frequency and the propagation constant of the SIEW are studied and compared to those of a conventional E- plane waveguide that has the same height and fill with the same substrate material. The cutoff frequency can be found from Fig. 7. As shown, the cutoff frequency of the SIEW with s = 0

3

Frequency (GHz)

Fig. 6. Insertion loss comparison between the conventional dielectric filled E-plane waveguide and the SIEW with W = 3.7 mm, D = 1 mm and

G = 0.5 mm

Frequency (GHz)

Fig. 7. Cutoff frequency comparison between the conventional dielectric filled E-plane waveguide and the SIEW with W = 3.7 mm, D = 1 mm and

G = 0.5 mm

mm is close to that of the conventional dielectric filled E-plane waveguide. With the s value increasing, the middle strips are inserted deeper into the waveguide and the cutoff frequency is lowered. It is because when the strips get into the waveguide, the SIEW behaves like a double ridge waveguide whose cutoff frequency is lower than that of the regular dielectric filled waveguide counterpart [25]. Consequently, the SIEW could operate in a lower frequency band and will allow a more compact design by increasing s. The use of such equivalent ridges to lower cutoff frequency is unique in the SIEW and is impossible to realize in the conventional SIW. The propagation constants of the SIEW are plotted and compared to that of the conventional dielectric filled E-plane waveguide in Fig. 8. It is found that the wave in SIEW propagates slower than in the conventional E-plane waveguide. This is the direct result of the lowered cutoff frequency in SIEW. In addition, the propagation constant increases with the middle strip insertion s. However, as frequency increases, the effects of the different s values on the propagation constant is reduced.

The effects of the through hole diameter D, the through hole gap g, and the SIEW width W are also studied. As seen in Fig. 9, the cutoff frequency is reduced with larger through

Frequency (GHz)

Fig. 8. Propagation constant comparison between the conventional dielectric filled E-plane waveguide and the SIEW with W = 3.7 mm, D = 1 mm and

G = 0.5 mm

Frequency (GHz)

Fig. 9. Effects of plated through hole diameter D on SIEW cutoff frequency with W = 3.7 mm, S = 0.3 mm and G = 0.5 mm

4

200

100

0

Frequency (GHz)

Frequency (GHz)

Fig. 11. Insertion loss comparison for different D values with W = 3.7 mm, S = 0.3 mm and G = 0.5 mm

holes. This is because a larger through hole pushes the middle strip deeper into the waveguide and thus reduces the cutoff frequency. As a result, the propagation constant increases with D as shown in Fig. 10. Similar to the middle strip insertion s, D has less affect on the propagation constant at a higher frequency. Insertion loss per substrate wavelength of the SIEW with different D values is plotted in Fig. 11. It is observed that larger through holes give less insertion loss. The through hole gap’s effects are plotted in Fig. 12 - 14. All the SIEW characteristics are not very sensitive to the through hole gap g. The cutoff frequency slightly reduces when g increases, as shown in Fig. 12, which results in slight increment of the propagation constant as shown in Fig. 13. Insertion loss is also stable for different g values as shown in Fig. 14. The SIEW width W ’s effects are demonstrated in Fig. 15 - 17. Based on Fig. 4(b), decreasing W results in deeper insertion of the middle strip into the waveguide, which lowers the cutoff frequency. Consequently, with W decreasing, the cutoff frequency is reduced as shown in Fig. 15 and the propagation constant is increased as shown in Fig. 16. In addition, Fig.

Frequency (GHz)

Fig. 12. Effects of plated through hole gap G on SIEW cutoff frequency with W = 3.7 mm, S = 0.3 mm and D = 1 mm

Frequency (GHz)

Fig. 13. Effects of plated through hole gap G on SIEW propagation constant with W = 3.7 mm, S = 0.3 mm and D = 1 mm

17 shows that a larger value of W results in lower insertion loss. The effects of the SIEW parameters on the waveguide performance are summarized in Table I, where ↑ means value increasing and ↓ means value decreasing.

As shown in Fig. 18, two cavity resonators at 8.35 GHz, one based on SIEW and the other one based on SIW, are analyzed using the HFSS eigenmode solver to obtain their Q factors. The Q factor depends on the cavity dimension and the substrate. For fair comparison, the two designs use the same substrate with ǫr = 13.3 and tanδ = 0.002, and have the similar cavity dimensions. For the SIEW cavity, D = 1 mm, g = 0.5 mm, s = 0.1 mm, W = 3.7 mm, and the substrate thickness is 5.08 mm. For the SIW cavity, D as well

TABLE I

SIEW PARAMETERS’ EFFECTS ON WAVEGUIDE PERFORMANCE

5

Frequency (GHz)

Fig. 15. Effects of SIEW width W on cutoff frequency with G = 0.5 mm, S = 0.3 mm and D = 1 mm

600SIEW, W=3.7 mm SIEW, W=4.7 mm

Frequency (GHz)

Fig. 17. Insertion loss comparison for different W values with G = 0.5 mm, S = 0.3 mm and D = 1 mm

Fig. 18. Geometry and electric field distribution of (a) an SIEW cavity resonator and (b) an SIW cavity resonator.

Frequency (GHz)

Fig. 19. Simulated PPHC with different copper strip thickness values, with W =3.7 mm, S=0.3 mm, D=1 mm and G=0.5 mm.

as g are the same as those of the SIEW cavity, W = 6 mm, and the substrate thickness is 2.5 mm. Both cavities have a volume of around 175 mm3. The simulated Q factors are 381 for the SIEW cavity and 385 for the SIW cavity. So, the SIEW performs similar to the SIW in terms of the Q factor.

Power handling of the SIEW depends on both the area and the electric field distribution of the transverse cross section. Given a PCB with fixed thickness, the peak power handling capacity (PPHC) increases with the SIEW width W because the transverse section area increases and it allows more power to pass through. Similarly, the PPHC decreases with through hole diameter D because a larger through hole effectively reduces the cross section area. With the middle strip insertion s increasing, the strips insert deeper into the SIEW. It pushes more power to the center of the SIEW, which effectively reduces the cross section area and lowers the PPHC. The thickness of the middle copper strip is another important parameter that determines the PPHC. For an SIEW made of 5.08 mm thick RT/Duroid 6010.2LM substrate whose dielectric strength is 474 V/mil, Fig. 19 shows the simulated PPHC with various strip thicknesses using Ansys HFSS. Reducing the thickness of the copper strip results in a stronger electric field at the strip’s edge, thus lowering PPHC.

IV. DESIGN EXAMPLES AND EXPERIMENTAL VALIDATION

In order to validate the SIEW concept, three SIEW circuits are designed, prototyped and measured.

Fig. 20. Simulation model of an SIEW with SMA-to-SIEW transitions

Fig. 20 shows the simulation model of the SIEW and the layout for the SMA-to-SIEW transition. The inner conductor of the SMA adapter is inserted into the middle layer of the SIEW to excite the horizontal electric field. The T-shape copper sheet is for the soldering of the SMA inner conductor and impedance matching. The top portion of the T-shape copper sheet is wider than the rest of the sheet. This design feature introduces additional capacitance between the SMA probe and the vertical waveguide wall, which cancels out the inductance caused by the SMA probe. Therefore it improves impedance matching. The circuit is 5.08 mm thick and is designed on RT/duroid 6010.2LM substrate. The substrate is an anisotropic material. However, only the dielectric constant and loss tangent in the z direction is provided in the data sheet as ǫrz = 10.7 and tanδz = 0.002. This is because most PCB applications excite predominantly the z directed electric field. In SIEW, the dielectric constant and loss tangent in the x and y directions are more important because the horizontal electric field is excited. The technical support of the PCB manufacturer suggests a dielectric constant of 13.3 in the circuit plane but cannot tell the difference in the x and y directions. The loss tangent in the circuit plane is not provided. Therefore, in our simulation model, ǫrx = ǫry = 13.3, ǫrz = 10.7, and tanδ = 0.002 are used. Such material parameter uncertainty may be the cause of the difference between simulated and measured results as described later.

The SIEW prototype is built by binding two PCB parts, each of 2.54 mm thick, as shown in Fig. 21. In Fig. 21(a), the middle layer is shown. All the through holes are copper plated. The cutouts of the substrate in the bottom part are for the housing of the SMA inner conductors. After the SMA inner connectors are soldered onto the T-shape copper sheets and a thin layer of solder is applied to the middle copper strips, the two PCB parts are stacked and bound together in a reflow oven. Next, the substrate cutouts are covered with copper tape to prevent energy leakage as shown in Fig. 21(b). The final prototype is measured using a vector network analyzer and shows an insertion loss of around 1 dB from 10.7 GHz to 12.1 GHz. The simulated and measured results are plotted in Fig. 22, which proves the SIEW is able to guide horizontally polarized waves.

Fig. 21. An SIEW (a) before and (b) after assembling.

Frequency (GHz)

Fig. 22. Simulated and measured S parameters of the SIEW in Fig. 21

The second example is a bandpass septum SIEW filter. The substrate is the same as in the previous example. It is designed following three steps. First, given the frequency pass band from f1 to f2 and the substrate relative permittivity ǫr, a conventional air filled E-plane waveguide filter in the √ǫrf1 to √ǫrf2 band is obtained using the procedure described in [15]. Next, the obtained septum dimension and spacing are used in the SIEW filter implementation. Lastly, the final design including the SMA-to-SIEW transitions is optimized using Ansys HFSS. The simulation model and the septum layout are illustrated in Fig. 23(a), where five pieces of septa are placed at the middle layer of the SIEW to form a bandpass filter. The filter prototype is shown in Fig. 23(b) and Fig. 23(c). Note that the septa are only printed on one PCB part to avoid septa displacement caused by the possible board misalignment during the binding process. The assembly procedure is the same as that of the SIEW as described before. The final filter prototype is measured and compared to the simulated results in Fig. 24. The measured minimum insertion loss is 2.65 dB that is about 0.7 dB less than the simulated one. The measured 3 dB bandwidth is 370 MHz from 11.06 to 11.43 GHz. It is about 80 MHz wider than the simulated one. The measured return loss is 16.5 dB in the pass band. There are three possible reasons that cause the discrepancy between simulated and measured results as observed in Fig. 24. The first is the material parameter

Fig. 23. An SIEW bandpass filter with (a) septum layout as well as its prototype (b) before and (c) after assembling.

Frequency (GHz)

Fig. 24. Simulated and measured S parameters of the SIEW filter.

uncertainty as discussed before. The second is the difficulty in simulating the thin layer of air gap between the two boards where the copper plating is removed. The last reason is the fabrication and assembly tolerance.

Although the SIEW is used to design an E-plane circuit to utilize horizontal polarization, it also supports vertical polarization as in the H-plane circuit. It is because the vertical polarization requires plated through holes as discussed in Section II and the SIEW inherits all the plated through holes from the SIW. So, the SIEW can be used to design dual polarized waveguide circuits which cannot be accomplished by using the conventional SIW. Recently, two dual polarized horn antennas on substrate were invented [26], [27] but each has its own limitation. In [26], a dielectric waveguide instead of a metallic waveguide is implemented to guide the horizontal polarization and so only high dielectric constant substrate can be used. In [27], the dual polarized horn section is implemented using the conventional ridged waveguide. The

Fig. 26. Middle layer layout of a dual polarized sectoral horn antenna.

substrate is completely cut through in the entire horn section to implement the vertical wall. As a result, a bulky metal housing is required to mechanically support the antenna, which makes it not light weight any more. The SIEW overcomes the above two drawbacks. It can be used on both high and low dielectric constant substrates and does not require a metal houseing.

Fig. 25 shows the prototype of a dual polarized sectoral horn antenna. It is built by stacking and binding two 2.54 mm thick Rogers TMM3 substrates with ǫrx = ǫry = 3.4, ǫrz = 3.45, and tanδ = 0.002. Fig. 26 shows the middle layout of the dual polarized antenna. It consists of an orthomode transducer (OMT) and a horn section with a dielectric load for impedance matching. The horizontal polarization is excited by the through port using the similar feeding structure as the two previous examples. The vertical polarization is excited by the orthogonal port using a probe of 2.54 mm long. Two small plated through holes, each with a diameter of 0.42 mm, are placed in the OMT. Their locations are labeled in the enlarged view in Fig. 26. The two plated through holes are inductive to the vertical polarization and reflect the vertical polarized signal. But to the horizontal polarization, they are capacitive and so are transparent to the horizontally polarized signal. Such polarization dependent characteristics of the two through holes can be illustrated and verified by the electric field distribution as shown in Fig. 27. All the other plated through holes have a diameter of 1 mm.

The antenna is designed and optimized using Ansys HFSS. The simulated and measured S parameters are plotted in Fig. 28. As shown, from 17.3 to 18.3 GHz, the return loss values of both the vertical and horizontal polarization ports are better than 10 dB and the port-to-port isolation is better than 20

Frequency (GHz)

Fig. 28. S parameters of the antenna in Fig. 25.

dB. The difference between the simulated and measured S parameters are mainly due to the PCB etching tolerance as well as the assembling tolerance that includes the imperfect alignment of the two parts and the possibly uneven soldering layer between the two parts. The antenna gain and efficiency are plotted in Fig. 29. The averaged gain values are at approximately 11.1 dB for the horizontal port and 10.2 dB for the vertical port. The antenna efficiencies are approximately 85% for the vertical polarization and 70% for the horizontal polarization at the middle of the band. The radiation patterns of the antenna are measured at 17.8 GHz in two principle planes for both the vertical and horizontal polarizations. They are plotted against the simulated ones in Fig. 30 - Fig. 33. As seen, the vertical polarization has a wider beam in the E-plane than H-plane while the horizontal polarization has a wider beam in the H-plane than E-plane. The measured cross polarization (X-pol) level is higher than the simulated one. Besides the fabrication and assembling tolerance of the antenna itself, there are three additional measurement factors that cause this. First, the nonzero X-pol of the transmitting antenna will increase the measured X-pol of the antenna under test. Second, the imperfect leveling of the antenna under test during measurement will increase the measured X-pol. Last, the scattering from the antenna’s mounting platform will also affect the measured X-pol.

Frequency (GHz)

Fig. 29. Gain and effciency of the antenna in Fig. 25.

Angle (degree)

Fig. 31. H-plane pattern at 17.8 GHz for vertical polarization excitation

Angle (degree)

Angle (degree)

V. CONCLUSIONS

A new transmission line type substrate integrated E-plane waveguide (SIEW) is presented and studied. It is used to design planar E-plane and dual polarized waveguide circuits on PCB. It adopts a row of copper plated through holes as well as a copper strip in the middle layer of the structure to emulate the vertical wall of an E-plane waveguide circuit. Both the two electric current components can flow on the synthesized vertical wall. A study of the SIEW parameters’ effects on the cutoff frequency, the propagation constant and the insertion loss is conducted. Numerical investigation reveals the copper strip needs to be inserted into the synthesized waveguide to effectively guide longitudinal current and achieve low insertion loss. In addition, it is found that a deeper insertion of the middle strip into the waveguide lowers the cutoff frequency and raises the propagation constant. The increasing of through hole diameter and the decreasing of SIEW width have the same effects because such changes push the middle strip deeper into the SIEW. The effects of the through hole gap is not as significant as other parameters. The power handling capacity of the SIEW is also discussed. Moreover, the SIEW is able to guide both the vertically and horizontally polarized signals simultaneously and can be used to design dual polarized waveguide circuits on PCB. As design examples, an SIEW with SMA-to-SIEW transitions, a bandpass septum SIEW

filter, and a dual polarized sectoral horn antenna are designed using Ansys HFSS. All three prototypes are built by stacking and binding two PCB parts in a reflow oven. The measured results validate the designs.

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Danyang Huang (S’15) was born in Guangzhou, China, in 1990. He received the B.S. degree in Physics from Inner Mongolia University of Technology, Huhhot, China, in 2013, and the M.S. degree in electrical engineering from Minnesota State University (MNSU), Mankato, MN, USA, in 2016. He is currently a Ph.D student in North Carolina State University. His research interest includes Substrate Integrated waveguide circuits and Direct Antenna Modulation. His Ph.D research topic is switching transients and parasitic effects in direct antenna

modulation.

Xuan Hui Wu (S’03-M’09-SM’15) received the B.Eng. degree in information science and electronic engineering from Zhejiang University, Hangzhou, China, in 2001, the M.Eng. degree in electrical engineering from National University of Singapore, Singapore, in 2005, and the Ph.D. degree from the University of Mississppi, Oxford, MS, in 2009.

From 2008 to 2010, he was an R&D antenna engineer at Radiowaves Inc., Billerica, MA. From 2010 to 2013, he was a microwave design engineer at General Dynamics Satcom Technologies, Newton,

NC. In 2013, he joined the faculty of the Minnesota State University, Mankato, MN, where he is currently an Associate Professor at the department of Electrical and Computer Engineering and Technology. His current research interests include the development of novel integrated waveguide circuits and antennas, MIMO antennas and computational electromagnetics. Dr. Wu is a member of the Phi Kappa Phi society.

Qun Zhang (M’99) received the B.S. degree from the Department of Optics in Shandong University in 1993, and the M.S. degree in Solid State Physics in the Institute of Crystal Materials, Shandong University in 1996. He received the Ph.D. degree in Electrical Engineering from the University of Virginia in 2001.

Since August 2000 he has worked in core R&D groups in companies including PhotonEx, Corvis (currently part of Level 3 Communications), and Tyco Telecommunications, mainly on modelling

(with experimental validation), simulation, and design of 40 Gb/s optical communication subsystems and systems. Dr. Zhang joined Minnesota State University, Mankato in 2006 and he is currently a Professor and the Chair in the Department of Electrical and Computer Engineering and Technology, Minnesota State University, Mankato, MN, USA. Dr. Zhang was a consulting engineer for Oclaro Inc. from 2010 to 2014, and was a technology consultant for Micropoint Bioscience Inc. from 2012 to 2015. He is a technology consultant for NeoPhotonics Corporation since 2016. Dr. Zhang is an expert on modeling and simulation of high speed electronic/photonic devices and communication systems. His current research interest includes Silicon Photonics, Coherent Optical communication, DSP/Machine Learning, and Photonic Design Automation. Dr. Zhang has published more than 40 research articles in international journals and conferences.